[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoney: clean up and update reset.c

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22439


Change subject: soc/amd/stoney: clean up and update reset.c
......................................................................

soc/amd/stoney: clean up and update reset.c

- Move #defines to soc/reset.h, add other reset definitions there.
- Clean up file to use definitions instead of magic numbers.
- Add do_soft_reset()
- Add do_global_reset() that powers the system completely off, then back
on.

BUG=b:69224851
TEST=Build gardenia; Build & boot

Change-Id: I0cc4c04b53b7fec38d45e962ff1292d8c717269c
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/soc/amd/stoneyridge/Makefile.inc
A src/soc/amd/stoneyridge/include/soc/reset.h
M src/soc/amd/stoneyridge/reset.c
3 files changed, 67 insertions(+), 15 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22439/1

diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 197145a..b5a8f38 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -42,6 +42,8 @@
 bootblock-y += bootblock/bootblock.c
 bootblock-y += early_setup.c
 bootblock-y += pmutil.c
+bootblock-y += reset.c
+bootblock-y += sb_util.c
 bootblock-y += tsc_freq.c
 
 romstage-y += BiosCallOuts.c
@@ -52,6 +54,8 @@
 romstage-y += gpio.c
 romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
 romstage-y += pmutil.c
+romstage-y += reset.c
+romstage-y += sb_util.c
 romstage-y += smbus.c
 romstage-y += smbus_spd.c
 romstage-y += ramtop.c
diff --git a/src/soc/amd/stoneyridge/include/soc/reset.h b/src/soc/amd/stoneyridge/include/soc/reset.h
new file mode 100644
index 0000000..d80c88a
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/reset.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AMDBLOCKS_RESET_H__
+#define __AMDBLOCKS_RESET_H__
+
+#define HT_INIT_CONTROL		0x6c
+#define   HTIC_BIOSR_DETECT	(1 << 5)
+
+/* IO 0xcf9 - Reset control port*/
+#define   FULL_RST		(1 << 3)
+#define   RST_CMD		(1 << 2)
+#define   SYS_RST		(1 << 1)
+
+/* PMx10 - Power Reset Config */
+#define PWR_RESET_CFG		0x10
+#define   TOGGLE_ALL_PWR_GOOD	(1 << 1)
+
+#endif	/* __AMDBLOCKS_RESET_H__ */
diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c
index 73f944d..f9e10b1 100644
--- a/src/soc/amd/stoneyridge/reset.c
+++ b/src/soc/amd/stoneyridge/reset.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2017 Google, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,29 +19,44 @@
 
 #include <arch/io.h>
 #include <reset.h>
+#include <soc/pci_devs.h>
+#include <soc/reset.h>
 #include <soc/southbridge.h>
 
-#define HT_INIT_CONTROL			0x6c
- #define HTIC_BIOSR_Detect		(1 << 5)
-
-
+/*
+ * Clearing bit 5 of HT_INIT_CONTROL signals that this reset came from the
+ * BIOS instead of some other reason.
+ */
 static void set_bios_reset(void)
 {
 	u32 htic;
-	htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
-	htic &= ~HTIC_BIOSR_Detect;
-	pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
+	htic = pci_io_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
+	htic &= ~HTIC_BIOSR_DETECT;
+	pci_io_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
+}
+
+void do_global_reset(void)
+{
+	set_bios_reset();
+
+	/* Place system in S5 state for 3 to 5 seconds. */
+	outb(RST_CMD | SYS_RST | FULL_RST, SYS_RESET);
 }
 
 void do_hard_reset(void)
 {
 	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/*
-	 * Actually it is not a real hard_reset
-	 *  --- it only reset coherent link table,
-	 *  but not reset link freq and width
-	 */
-	outb((0 << 3) | (0 << 2) | (1 << 1), SYS_RESET);
-	outb((0 << 3) | (1 << 2) | (1 << 1), SYS_RESET);
+
+	/* De-assert and then assert all PwrGood signals on CF9 reset. */
+	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | \
+			TOGGLE_ALL_PWR_GOOD);
+	outb( RST_CMD | SYS_RST, SYS_RESET);
+}
+
+void do_soft_reset(void)
+{
+	set_bios_reset();
+
+	/* Assert reset signals only. */
+	outb(RST_CMD | SYS_RST, SYS_RESET);
 }

-- 
To view, visit https://review.coreboot.org/22439
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0cc4c04b53b7fec38d45e962ff1292d8c717269c
Gerrit-Change-Number: 22439
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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