<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22439">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoney: clean up and update reset.c<br><br>- Move #defines to soc/reset.h, add other reset definitions there.<br>- Clean up file to use definitions instead of magic numbers.<br>- Add do_soft_reset()<br>- Add do_global_reset() that powers the system completely off, then back<br>on.<br><br>BUG=b:69224851<br>TEST=Build gardenia; Build & boot<br><br>Change-Id: I0cc4c04b53b7fec38d45e962ff1292d8c717269c<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/soc/amd/stoneyridge/Makefile.inc<br>A src/soc/amd/stoneyridge/include/soc/reset.h<br>M src/soc/amd/stoneyridge/reset.c<br>3 files changed, 67 insertions(+), 15 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22439/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc<br>index 197145a..b5a8f38 100644<br>--- a/src/soc/amd/stoneyridge/Makefile.inc<br>+++ b/src/soc/amd/stoneyridge/Makefile.inc<br>@@ -42,6 +42,8 @@<br> bootblock-y += bootblock/bootblock.c<br> bootblock-y += early_setup.c<br> bootblock-y += pmutil.c<br>+bootblock-y += reset.c<br>+bootblock-y += sb_util.c<br> bootblock-y += tsc_freq.c<br> <br> romstage-y += BiosCallOuts.c<br>@@ -52,6 +54,8 @@<br> romstage-y += gpio.c<br> romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c<br> romstage-y += pmutil.c<br>+romstage-y += reset.c<br>+romstage-y += sb_util.c<br> romstage-y += smbus.c<br> romstage-y += smbus_spd.c<br> romstage-y += ramtop.c<br>diff --git a/src/soc/amd/stoneyridge/include/soc/reset.h b/src/soc/amd/stoneyridge/include/soc/reset.h<br>new file mode 100644<br>index 0000000..d80c88a<br>--- /dev/null<br>+++ b/src/soc/amd/stoneyridge/include/soc/reset.h<br>@@ -0,0 +1,32 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __AMDBLOCKS_RESET_H__<br>+#define __AMDBLOCKS_RESET_H__<br>+<br>+#define HT_INIT_CONTROL 0x6c<br>+#define HTIC_BIOSR_DETECT (1 << 5)<br>+<br>+/* IO 0xcf9 - Reset control port*/<br>+#define FULL_RST (1 << 3)<br>+#define RST_CMD (1 << 2)<br>+#define SYS_RST (1 << 1)<br>+<br>+/* PMx10 - Power Reset Config */<br>+#define PWR_RESET_CFG 0x10<br>+#define TOGGLE_ALL_PWR_GOOD (1 << 1)<br>+<br>+#endif /* __AMDBLOCKS_RESET_H__ */<br>diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c<br>index 73f944d..f9e10b1 100644<br>--- a/src/soc/amd/stoneyridge/reset.c<br>+++ b/src/soc/amd/stoneyridge/reset.c<br>@@ -2,6 +2,7 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright (C) 2010 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2017 Google, Inc.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -18,29 +19,44 @@<br> <br> #include <arch/io.h><br> #include <reset.h><br>+#include <soc/pci_devs.h><br>+#include <soc/reset.h><br> #include <soc/southbridge.h><br> <br>-#define HT_INIT_CONTROL 0x6c<br>- #define HTIC_BIOSR_Detect (1 << 5)<br>-<br>-<br>+/*<br>+ * Clearing bit 5 of HT_INIT_CONTROL signals that this reset came from the<br>+ * BIOS instead of some other reason.<br>+ */<br> static void set_bios_reset(void)<br> {<br> u32 htic;<br>- htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);<br>- htic &= ~HTIC_BIOSR_Detect;<br>- pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);<br>+ htic = pci_io_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);<br>+ htic &= ~HTIC_BIOSR_DETECT;<br>+ pci_io_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);<br>+}<br>+<br>+void do_global_reset(void)<br>+{<br>+ set_bios_reset();<br>+<br>+ /* Place system in S5 state for 3 to 5 seconds. */<br>+ outb(RST_CMD | SYS_RST | FULL_RST, SYS_RESET);<br> }<br> <br> void do_hard_reset(void)<br> {<br> set_bios_reset();<br>- /* Try rebooting through port 0xcf9 */<br>- /*<br>- * Actually it is not a real hard_reset<br>- * --- it only reset coherent link table,<br>- * but not reset link freq and width<br>- */<br>- outb((0 << 3) | (0 << 2) | (1 << 1), SYS_RESET);<br>- outb((0 << 3) | (1 << 2) | (1 << 1), SYS_RESET);<br>+<br>+ /* De-assert and then assert all PwrGood signals on CF9 reset. */<br>+ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | \<br>+ TOGGLE_ALL_PWR_GOOD);<br>+ outb( RST_CMD | SYS_RST, SYS_RESET);<br>+}<br>+<br>+void do_soft_reset(void)<br>+{<br>+ set_bios_reset();<br>+<br>+ /* Assert reset signals only. */<br>+ outb(RST_CMD | SYS_RST, SYS_RESET);<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/22439">change 22439</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22439"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0cc4c04b53b7fec38d45e962ff1292d8c717269c </div>
<div style="display:none"> Gerrit-Change-Number: 22439 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>