[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Replace BIT(n) in southbridge

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22427


Change subject: amd/stoneyridge: Replace BIT(n) in southbridge
......................................................................

amd/stoneyridge: Replace BIT(n) in southbridge

Use more descriptive #define values for the ACPI features and
register decoding.

Change-Id: Iaaf9f9bd5761001bc4bfe6b64a6c72b1f04844bd
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/southbridge.c
1 file changed, 5 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/22427/1

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 0d96b5f..6ab0678 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -61,10 +61,11 @@
 		pm_write16(PM_ACPI_SMI_CMD, 0);
 	}
 
-	/* AcpiDecodeEnable, When set, SB uses the contents of the PM registers
-	 * at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn
-	 */
-	pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2));
+	/* Decode ACPI registers and enable standard features */
+	pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD |
+				PM_ACPI_GLOBAL_EN |
+				PM_ACPI_RTC_EN_EN |
+				PM_ACPI_TIMER_EN_EN);
 }
 
 void southbridge_init(void *chip_info)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iaaf9f9bd5761001bc4bfe6b64a6c72b1f04844bd
Gerrit-Change-Number: 22427
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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