[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Fix DRAM clear check

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22424


Change subject: amd/stoneyridge: Fix DRAM clear check
......................................................................

amd/stoneyridge: Fix DRAM clear check

Add appropriate #include files to romstage.c to ensure sizes of the
devicetree structures are correct.  This fixes a bug where dev->chip_info
is incorrectly detected as 0.

Also shorten a printk string to bring the source line within 80 columns.

Change-Id: I1ed51cdbb8df387a453de6cb944b90538dac4431
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/romstage.c
1 file changed, 3 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/22424/1

diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 9b22761..f54eafe 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -21,6 +21,8 @@
 #include <cbmem.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
+#include <device/device.h>
+#include <chip.h>
 #include <program_loading.h>
 #include <agesawrapper.h>
 #include <agesawrapper_call.h>
@@ -118,7 +120,7 @@
 	const struct device *dev = dev_find_slot(0, GNB_DEVFN);
 
 	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "ERROR: Could not find SoC devicetree config\n");
+		printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n");
 		return;
 	}
 

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1ed51cdbb8df387a453de6cb944b90538dac4431
Gerrit-Change-Number: 22424
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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