[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Make use of Intel SPI common block

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22364


Change subject: soc/intel/apollolake: Make use of Intel SPI common block
......................................................................

soc/intel/apollolake: Make use of Intel SPI common block

TEST=Build and boot reef

Change-Id: I1bb22ef1737b9e35892294ec0d66df39c546d72e
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/Makefile.inc
D src/soc/intel/apollolake/spi.c
3 files changed, 1 insertion(+), 32 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/22364/1

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index cf2492c..f568799 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -86,6 +86,7 @@
 	select SOC_INTEL_COMMON_BLOCK_XDCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_SMM
+	select SOC_INTEL_COMMON_BLOCK_SPI
 	select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index c295e36..5e9e5cb 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -15,7 +15,6 @@
 bootblock-y += lpc.c
 bootblock-y += mmap_boot.c
 bootblock-y += pmutil.c
-bootblock-y += spi.c
 bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
 
@@ -34,12 +33,10 @@
 romstage-y += mmap_boot.c
 romstage-y += pmutil.c
 romstage-y += reset.c
-romstage-y += spi.c
 
 smm-y += mmap_boot.c
 smm-y += pmutil.c
 smm-y += smihandler.c
-smm-y += spi.c
 smm-y += uart_early.c
 smm-y += uart.c
 
@@ -58,18 +55,15 @@
 ramstage-y += uart.c
 ramstage-y += nhlt.c
 ramstage-y += systemagent.c
-ramstage-y += spi.c
 ramstage-y += pmutil.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += sram.c
-ramstage-y += spi.c
 ramstage-y += xdci.c
 ramstage-y += sd.c
 
 postcar-y += memmap.c
 postcar-y += mmap_boot.c
-postcar-y += spi.c
 postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 
 postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
@@ -82,7 +76,6 @@
 verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 verstage-y += pmutil.c
 verstage-y += reset.c
-verstage-y += spi.c
 
 ifeq ($(CONFIG_SOC_INTEL_GLK),y)
 bootblock-y += gpio_glk.c
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c
deleted file mode 100644
index 9a651ee..0000000
--- a/src/soc/intel/apollolake/spi.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <intelblocks/fast_spi.h>
-#include <spi-generic.h>
-
-const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
-	{ .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
-};
-
-const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1bb22ef1737b9e35892294ec0d66df39c546d72e
Gerrit-Change-Number: 22364
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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