<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22364">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Make use of Intel SPI common block<br><br>TEST=Build and boot reef<br><br>Change-Id: I1bb22ef1737b9e35892294ec0d66df39c546d72e<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/apollolake/Kconfig<br>M src/soc/intel/apollolake/Makefile.inc<br>D src/soc/intel/apollolake/spi.c<br>3 files changed, 1 insertion(+), 32 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/22364/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig<br>index cf2492c..f568799 100644<br>--- a/src/soc/intel/apollolake/Kconfig<br>+++ b/src/soc/intel/apollolake/Kconfig<br>@@ -86,6 +86,7 @@<br> select SOC_INTEL_COMMON_BLOCK_XDCI<br> select SOC_INTEL_COMMON_BLOCK_XHCI<br> select SOC_INTEL_COMMON_BLOCK_SMM<br>+ select SOC_INTEL_COMMON_BLOCK_SPI<br> select SOC_INTEL_COMMON_SPI_FLASH_PROTECT<br> select UDELAY_TSC<br> select TSC_CONSTANT_RATE<br>diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc<br>index c295e36..5e9e5cb 100644<br>--- a/src/soc/intel/apollolake/Makefile.inc<br>+++ b/src/soc/intel/apollolake/Makefile.inc<br>@@ -15,7 +15,6 @@<br> bootblock-y += lpc.c<br> bootblock-y += mmap_boot.c<br> bootblock-y += pmutil.c<br>-bootblock-y += spi.c<br> bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c<br> bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S<br> <br>@@ -34,12 +33,10 @@<br> romstage-y += mmap_boot.c<br> romstage-y += pmutil.c<br> romstage-y += reset.c<br>-romstage-y += spi.c<br> <br> smm-y += mmap_boot.c<br> smm-y += pmutil.c<br> smm-y += smihandler.c<br>-smm-y += spi.c<br> smm-y += uart_early.c<br> smm-y += uart.c<br> <br>@@ -58,18 +55,15 @@<br> ramstage-y += uart.c<br> ramstage-y += nhlt.c<br> ramstage-y += systemagent.c<br>-ramstage-y += spi.c<br> ramstage-y += pmutil.c<br> ramstage-y += pmc.c<br> ramstage-y += reset.c<br> ramstage-y += sram.c<br>-ramstage-y += spi.c<br> ramstage-y += xdci.c<br> ramstage-y += sd.c<br> <br> postcar-y += memmap.c<br> postcar-y += mmap_boot.c<br>-postcar-y += spi.c<br> postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c<br> <br> postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S<br>@@ -82,7 +76,6 @@<br> verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c<br> verstage-y += pmutil.c<br> verstage-y += reset.c<br>-verstage-y += spi.c<br> <br> ifeq ($(CONFIG_SOC_INTEL_GLK),y)<br> bootblock-y += gpio_glk.c<br>diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c<br>deleted file mode 100644<br>index 9a651ee..0000000<br>--- a/src/soc/intel/apollolake/spi.c<br>+++ /dev/null<br>@@ -1,25 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright 2016 Google Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <intelblocks/fast_spi.h><br>-#include <spi-generic.h><br>-<br>-const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {<br>- { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },<br>-};<br>-<br>-const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);<br></pre><p>To view, visit <a href="https://review.coreboot.org/22364">change 22364</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22364"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1bb22ef1737b9e35892294ec0d66df39c546d72e </div>
<div style="display:none"> Gerrit-Change-Number: 22364 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>