[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x: Clarify the raminit memory mapping
Arthur Heymans (Code Review)
gerrit at coreboot.org
Sat Nov 4 10:15:54 CET 2017
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22328
Change subject: nb/intel/x4x: Clarify the raminit memory mapping
......................................................................
nb/intel/x4x: Clarify the raminit memory mapping
This replaces magic values by macros and adds some comments to improve
readability.
Channel 1, rank 3 is now changed. It seems not to have been used,
which is why code worked fine with it being wrong.
Change-Id: I58923e4a8a756f4ae65f759e7d46e03fad39fab7
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/x4x/raminit_ddr2.c
M src/northbridge/intel/x4x/x4x.h
2 files changed, 84 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/22328/1
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index c427f63..90912ad 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -982,6 +982,70 @@
}
}
+static void pre_jedec_memory_map(void)
+{
+ /*
+ * Configure the memory mapping in stacked mode (channel 1 being mapped
+ * above channel 0) and with 128M per rank.
+ * This simplyfies dram trainings a lot since those need a test address.
+ *
+ * +-------------+ => 0
+ * | ch 0, rank 0|
+ * +-------------+ => 0x8000000 (128M)
+ * | ch 0, rank 1|
+ * +-------------+ => 0x10000000 (256M)
+ * | ch 0, rank 2|
+ * +-------------+ => 0x18000000 (384M)
+ * | ch 0, rank 3|
+ * +-------------+ => 0x20000000 (512M)
+ * | ch 1, rank 0|
+ * +-------------+ => 0x28000000 (640M)
+ * | ch 1, rank 1|
+ * +-------------+ => 0x30000000 (768M)
+ * | ch 1, rank 2|
+ * +-------------+ => 0x38000000 (896M)
+ * | ch 1, rank 3|
+ * +-------------+
+ *
+ * After all trainings are done this is set to the real values specified
+ * by the SPD.
+ */
+ /* Set rank 0-3 populated */
+ MCHBAR32(C0CKECTRL) = (MCHBAR32(C0CKECTRL) & ~1) | 0xf00000;
+ MCHBAR32(C1CKECTRL) = (MCHBAR32(C1CKECTRL) & ~1) | 0xf00000;
+ /* Set size of each rank to 128M */
+ MCHBAR16(C0DRA01) = 0x0101;
+ MCHBAR16(C0DRA23) = 0x0101;
+ MCHBAR16(C1DRA01) = 0x0101;
+ MCHBAR16(C1DRA23) = 0x0101;
+ MCHBAR16(C0DRB0) = 0x0002;
+ MCHBAR16(C0DRB1) = 0x0004;
+ MCHBAR16(C0DRB2) = 0x0006;
+ MCHBAR16(C0DRB3) = 0x0008;
+ MCHBAR16(C0DRB0) = 0x0002;
+ MCHBAR16(C0DRB1) = 0x0004;
+ MCHBAR16(C0DRB2) = 0x0006;
+ MCHBAR16(C0DRB3) = 0x0008;
+ MCHBAR16(C1DRB0) = 0x0002;
+ MCHBAR16(C1DRB1) = 0x0004;
+ MCHBAR16(C1DRB2) = 0x0006;
+ MCHBAR16(C1DRB3) = 0x0008;
+ MCHBAR8(0x111) = MCHBAR8(0x111) | STACKED_MEM;
+ MCHBAR32(0x104) = 0;
+ MCHBAR16(0x102) = 0x400;
+ MCHBAR8(0x100) = (2 << 5) | (3 << 3);
+ MCHBAR16(0x10e) = 0;
+ MCHBAR32(0x108) = 0;
+ pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, 0x4000);
+ /* TOM(64M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */
+ pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, 0x10);
+ /* TOUUD(1M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */
+ pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, 0x0400);
+ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_GBSM, 0x40000000);
+ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_BGSM, 0x40000000);
+ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_TSEG, 0x40000000);
+}
+
static void dojedec_ddr2(u8 r, u8 ch, u8 cmd, u16 val)
{
u32 addr = (ch << 29) | (r*0x08000000);
@@ -1527,27 +1591,7 @@
printk(BIOS_DEBUG, "Done RCOMP update\n");
}
- // Set defaults
- MCHBAR32(0x260) = (MCHBAR32(0x260) & ~1) | 0xf00000;
- MCHBAR32(0x660) = (MCHBAR32(0x660) & ~1) | 0xf00000;
- MCHBAR32(0x208) = 0x01010101;
- MCHBAR32(0x608) = 0x01010101;
- MCHBAR32(0x200) = 0x00040002;
- MCHBAR32(0x204) = 0x00080006;
- MCHBAR32(0x600) = 0x00040002;
- MCHBAR32(0x604) = 0x00100006;
- MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2;
- MCHBAR32(0x104) = 0;
- MCHBAR16(0x102) = 0x400;
- MCHBAR8(0x100) = (2 << 5) | (3 << 3);
- MCHBAR16(0x10e) = 0;
- MCHBAR32(0x108) = 0;
- pci_write_config16(PCI_DEV(0, 0, 0), 0xb0, 0x4000);
- pci_write_config16(PCI_DEV(0, 0, 0), 0xa0, 0x0010);
- pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, 0x0400);
- pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, 0x40000000);
- pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, 0x40000000);
- pci_write_config32(PCI_DEV(0, 0, 0), 0xac, 0x40000000);
+ pre_jedec_memory_map();
// IOBUFACT
if (CHANNEL_IS_POPULATED(s->dimms, 0)) {
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 0995435..eaec7c6 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -86,6 +86,25 @@
#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
+#define CHDECMISC 0x111
+#define STACKED_MEM (1 << 1)
+
+#define C0DRB0 0x200
+#define C0DRB1 0x202
+#define C0DRB2 0x204
+#define C0DRB3 0x206
+#define C0DRA01 0x208
+#define C0DRA23 0x20a
+#define C0CKECTRL 0x260
+
+#define C1DRB0 0x600
+#define C1DRB1 0x602
+#define C1DRB2 0x604
+#define C1DRB3 0x606
+#define C1DRA01 0x608
+#define C1DRA23 0x60a
+#define C1CKECTRL 0x660
+
#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */
#define PMSTS_WARM_RESET (1 << 8)
#define PMSTS_BOTH_SELFREFRESH (3 << 0)
--
To view, visit https://review.coreboot.org/22328
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I58923e4a8a756f4ae65f759e7d46e03fad39fab7
Gerrit-Change-Number: 22328
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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