<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22328">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/x4x: Clarify the raminit memory mapping<br><br>This replaces magic values by macros and adds some comments to improve<br>readability.<br><br>Channel 1, rank 3 is now changed. It seems not to have been used,<br>which is why code worked fine with it being wrong.<br><br>Change-Id: I58923e4a8a756f4ae65f759e7d46e03fad39fab7<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/x4x/raminit_ddr2.c<br>M src/northbridge/intel/x4x/x4x.h<br>2 files changed, 84 insertions(+), 21 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/22328/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c<br>index c427f63..90912ad 100644<br>--- a/src/northbridge/intel/x4x/raminit_ddr2.c<br>+++ b/src/northbridge/intel/x4x/raminit_ddr2.c<br>@@ -982,6 +982,70 @@<br> }<br> }<br> <br>+static void pre_jedec_memory_map(void)<br>+{<br>+ /*<br>+ * Configure the memory mapping in stacked mode (channel 1 being mapped<br>+ * above channel 0) and with 128M per rank.<br>+ * This simplyfies dram trainings a lot since those need a test address.<br>+ *<br>+ * +-------------+ => 0<br>+ * | ch 0, rank 0|<br>+ * +-------------+ => 0x8000000 (128M)<br>+ * | ch 0, rank 1|<br>+ * +-------------+ => 0x10000000 (256M)<br>+ * | ch 0, rank 2|<br>+ * +-------------+ => 0x18000000 (384M)<br>+ * | ch 0, rank 3|<br>+ * +-------------+ => 0x20000000 (512M)<br>+ * | ch 1, rank 0|<br>+ * +-------------+ => 0x28000000 (640M)<br>+ * | ch 1, rank 1|<br>+ * +-------------+ => 0x30000000 (768M)<br>+ * | ch 1, rank 2|<br>+ * +-------------+ => 0x38000000 (896M)<br>+ * | ch 1, rank 3|<br>+ * +-------------+<br>+ *<br>+ * After all trainings are done this is set to the real values specified<br>+ * by the SPD.<br>+ */<br>+ /* Set rank 0-3 populated */<br>+ MCHBAR32(C0CKECTRL) = (MCHBAR32(C0CKECTRL) & ~1) | 0xf00000;<br>+ MCHBAR32(C1CKECTRL) = (MCHBAR32(C1CKECTRL) & ~1) | 0xf00000;<br>+ /* Set size of each rank to 128M */<br>+ MCHBAR16(C0DRA01) = 0x0101;<br>+ MCHBAR16(C0DRA23) = 0x0101;<br>+ MCHBAR16(C1DRA01) = 0x0101;<br>+ MCHBAR16(C1DRA23) = 0x0101;<br>+ MCHBAR16(C0DRB0) = 0x0002;<br>+ MCHBAR16(C0DRB1) = 0x0004;<br>+ MCHBAR16(C0DRB2) = 0x0006;<br>+ MCHBAR16(C0DRB3) = 0x0008;<br>+ MCHBAR16(C0DRB0) = 0x0002;<br>+ MCHBAR16(C0DRB1) = 0x0004;<br>+ MCHBAR16(C0DRB2) = 0x0006;<br>+ MCHBAR16(C0DRB3) = 0x0008;<br>+ MCHBAR16(C1DRB0) = 0x0002;<br>+ MCHBAR16(C1DRB1) = 0x0004;<br>+ MCHBAR16(C1DRB2) = 0x0006;<br>+ MCHBAR16(C1DRB3) = 0x0008;<br>+ MCHBAR8(0x111) = MCHBAR8(0x111) | STACKED_MEM;<br>+ MCHBAR32(0x104) = 0;<br>+ MCHBAR16(0x102) = 0x400;<br>+ MCHBAR8(0x100) = (2 << 5) | (3 << 3);<br>+ MCHBAR16(0x10e) = 0;<br>+ MCHBAR32(0x108) = 0;<br>+ pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, 0x4000);<br>+ /* TOM(64M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */<br>+ pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, 0x10);<br>+ /* TOUUD(1M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */<br>+ pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, 0x0400);<br>+ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_GBSM, 0x40000000);<br>+ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_BGSM, 0x40000000);<br>+ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_TSEG, 0x40000000);<br>+}<br>+<br> static void dojedec_ddr2(u8 r, u8 ch, u8 cmd, u16 val)<br> {<br> u32 addr = (ch << 29) | (r*0x08000000);<br>@@ -1527,27 +1591,7 @@<br> printk(BIOS_DEBUG, "Done RCOMP update\n");<br> }<br> <br>- // Set defaults<br>- MCHBAR32(0x260) = (MCHBAR32(0x260) & ~1) | 0xf00000;<br>- MCHBAR32(0x660) = (MCHBAR32(0x660) & ~1) | 0xf00000;<br>- MCHBAR32(0x208) = 0x01010101;<br>- MCHBAR32(0x608) = 0x01010101;<br>- MCHBAR32(0x200) = 0x00040002;<br>- MCHBAR32(0x204) = 0x00080006;<br>- MCHBAR32(0x600) = 0x00040002;<br>- MCHBAR32(0x604) = 0x00100006;<br>- MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2;<br>- MCHBAR32(0x104) = 0;<br>- MCHBAR16(0x102) = 0x400;<br>- MCHBAR8(0x100) = (2 << 5) | (3 << 3);<br>- MCHBAR16(0x10e) = 0;<br>- MCHBAR32(0x108) = 0;<br>- pci_write_config16(PCI_DEV(0, 0, 0), 0xb0, 0x4000);<br>- pci_write_config16(PCI_DEV(0, 0, 0), 0xa0, 0x0010);<br>- pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, 0x0400);<br>- pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, 0x40000000);<br>- pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, 0x40000000);<br>- pci_write_config32(PCI_DEV(0, 0, 0), 0xac, 0x40000000);<br>+ pre_jedec_memory_map();<br> <br> // IOBUFACT<br> if (CHANNEL_IS_POPULATED(s->dimms, 0)) {<br>diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h<br>index 0995435..eaec7c6 100644<br>--- a/src/northbridge/intel/x4x/x4x.h<br>+++ b/src/northbridge/intel/x4x/x4x.h<br>@@ -86,6 +86,25 @@<br> #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))<br> #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))<br> <br>+#define CHDECMISC 0x111<br>+#define STACKED_MEM (1 << 1)<br>+<br>+#define C0DRB0 0x200<br>+#define C0DRB1 0x202<br>+#define C0DRB2 0x204<br>+#define C0DRB3 0x206<br>+#define C0DRA01 0x208<br>+#define C0DRA23 0x20a<br>+#define C0CKECTRL 0x260<br>+<br>+#define C1DRB0 0x600<br>+#define C1DRB1 0x602<br>+#define C1DRB2 0x604<br>+#define C1DRB3 0x606<br>+#define C1DRA01 0x608<br>+#define C1DRA23 0x60a<br>+#define C1CKECTRL 0x660<br>+<br> #define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */<br> #define PMSTS_WARM_RESET (1 << 8)<br> #define PMSTS_BOTH_SELFREFRESH (3 << 0)<br></pre><p>To view, visit <a href="https://review.coreboot.org/22328">change 22328</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22328"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I58923e4a8a756f4ae65f759e7d46e03fad39fab7 </div>
<div style="display:none"> Gerrit-Change-Number: 22328 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>