[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Remove fixme.c
Marshall Dawson (Code Review)
gerrit at coreboot.org
Thu Nov 2 18:00:52 CET 2017
Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22297
Change subject: amd/stoneyridge: Remove fixme.c
......................................................................
amd/stoneyridge: Remove fixme.c
Move the two functions in fixme.c to places where they make more sense.
Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem()
instead of explicitely reading the MSR.
BUG=b:62241048
Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/common/agesawrapper.h
M src/soc/amd/stoneyridge/Makefile.inc
M src/soc/amd/stoneyridge/bootblock/bootblock.c
D src/soc/amd/stoneyridge/fixme.c
M src/soc/amd/stoneyridge/northbridge.c
5 files changed, 59 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/22297/1
diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/agesawrapper.h
index b42f531..3b925b2 100644
--- a/src/soc/amd/common/agesawrapper.h
+++ b/src/soc/amd/common/agesawrapper.h
@@ -51,7 +51,6 @@
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
VOID amd_initcpuio(void);
-VOID amd_initmmio(void);
const void *agesawrapper_locate_module(const CHAR8 name[8]);
void OemPostParams(AMD_POST_PARAMS *PostParams);
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 78ece2e..85452c4 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -39,7 +39,6 @@
bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
bootblock-y += BiosCallOuts.c
-bootblock-y += fixme.c
bootblock-y += bootblock/bootblock.c
bootblock-y += early_setup.c
bootblock-y += pmutil.c
@@ -50,7 +49,6 @@
romstage-y += early_setup.c
romstage-y += dimmSpd.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
-romstage-y += fixme.c
romstage-y += gpio.c
romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
romstage-y += pmutil.c
@@ -73,7 +71,6 @@
ramstage-y += cpu.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
-ramstage-y += fixme.c
ramstage-y += gpio.c
ramstage-y += hda.c
ramstage-y += southbridge.c
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 1712b51..2c8d335 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -17,11 +17,16 @@
#include <stdint.h>
#include <assert.h>
#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/amdfam15.h>
#include <smp/node.h>
#include <bootblock_common.h>
#include <agesawrapper.h>
#include <agesawrapper_call.h>
#include <soc/southbridge.h>
+
+#define ROM_BASE ((uintptr_t)(0x100000000ull - CONFIG_ROM_SIZE))
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
@@ -37,6 +42,26 @@
bootblock_main_with_timestamp(base_timestamp);
}
+/* Set the MMIO Configuration Base Address and Bus Range. */
+static void amd_initmmio(void)
+{
+ msr_t mmconf;
+ msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+ int rom_mtrr;
+
+ mmconf.hi = 0;
+ mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN;
+ mmconf.lo |= (fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT);
+ wrmsr(MMIO_CONF_BASE, mmconf);
+
+ /*
+ * todo: AGESA currently writes variable MTRRs. Once that is
+ * corrected, un-hardcode this MTRR.
+ */
+ rom_mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2;
+ set_var_mtrr(rom_mtrr, ROM_BASE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+}
+
void bootblock_soc_early_init(void)
{
amd_initmmio();
diff --git a/src/soc/amd/stoneyridge/fixme.c b/src/soc/amd/stoneyridge/fixme.c
deleted file mode 100644
index 48344f1..0000000
--- a/src/soc/amd/stoneyridge/fixme.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/lapic_def.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/amdfam15.h>
-#include <soc/pci_devs.h>
-#include <soc/pci_devs.h>
-#include <soc/northbridge.h>
-#include <soc/southbridge.h>
-#include <agesawrapper.h>
-
-#define ROM_BASE ((uintptr_t)(0x100000000ull - CONFIG_ROM_SIZE))
-
-/*
- * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,
- * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining
- * MMIO to posted. Route all I/O to the southbridge.
- */
-void amd_initcpuio(void)
-{
- msr_t topmem = rdmsr(TOP_MEM); /* todo: build bsp_topmem() earlier */
- u32 base, limit;
-
- /* Enable legacy video routing: D18F1xF4 VGA Enable */
- pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
-
- /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */
- base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;
- limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;
- pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
- pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
-
- /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */
- base = (topmem.lo >> 8) | MMIO_WE | MMIO_RE;
- limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
- pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO + 8, limit);
- pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO + 8, base);
-
- /* Send all I/O (0000-0xffff) to southbridge */
- base = 0 | MMIO_WE | MMIO_RE;
- limit = ALIGN_DOWN(0xffff, 4 * KiB);
- pci_write_config32(SOC_ADDR_DEV, D18F1_IO_LIMIT0, limit);
- pci_write_config32(SOC_ADDR_DEV, D18F1_IO_BASE0, base);
-}
-
-/* Set the MMIO Configuration Base Address and Bus Range. */
-void amd_initmmio(void)
-{
- msr_t mmconf;
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
- int rom_mtrr;
-
- mmconf.hi = 0;
- mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN;
- mmconf.lo |= (fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT);
- wrmsr(MMIO_CONF_BASE, mmconf);
-
- /*
- * todo: AGESA currently writes variable MTRRs. Once that is
- * corrected, un-hardcode this MTRR.
- */
- rom_mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2;
- set_var_mtrr(rom_mtrr, ROM_BASE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
-}
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 39001af..4716a10 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -22,6 +22,7 @@
#include <console/console.h>
#include <cpu/amd/mtrr.h>
#include <cpu/cpu.h>
+#include <cpu/x86/lapic_def.h>
#include <cpu/x86/msr.h>
#include <device/device.h>
#include <device/pci.h>
@@ -29,6 +30,7 @@
#include <agesawrapper.h>
#include <agesawrapper_call.h>
#include <soc/northbridge.h>
+#include <soc/southbridge.h>
#include <soc/pci_devs.h>
#include <stdint.h>
#include <stdlib.h>
@@ -334,6 +336,38 @@
.device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT,
};
+/*
+ * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,
+ * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining
+ * MMIO to posted. Route all I/O to the southbridge.
+ */
+void amd_initcpuio(void)
+{
+ u32 topmem = (u32)bsp_topmem();
+ u32 base, limit;
+
+ /* Enable legacy video routing: D18F1xF4 VGA Enable */
+ pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
+
+ /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */
+ base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;
+ limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;
+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
+
+ /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */
+ base = (topmem >> 8) | MMIO_WE | MMIO_RE;
+ limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO + 8, limit);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO + 8, base);
+
+ /* Send all I/O (0000-0xffff) to southbridge */
+ base = 0 | MMIO_WE | MMIO_RE;
+ limit = ALIGN_DOWN(0xffff, 4 * KiB);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_IO_LIMIT0, limit);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_IO_BASE0, base);
+}
+
void fam15_finalize(void *chip_info)
{
device_t dev;
--
To view, visit https://review.coreboot.org/22297
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3
Gerrit-Change-Number: 22297
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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