<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22297">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Remove fixme.c<br><br>Move the two functions in fixme.c to places where they make more sense.<br>Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem()<br>instead of explicitely reading the MSR.<br><br>BUG=b:62241048<br><br>Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/common/agesawrapper.h<br>M src/soc/amd/stoneyridge/Makefile.inc<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>D src/soc/amd/stoneyridge/fixme.c<br>M src/soc/amd/stoneyridge/northbridge.c<br>5 files changed, 59 insertions(+), 85 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/22297/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/agesawrapper.h<br>index b42f531..3b925b2 100644<br>--- a/src/soc/amd/common/agesawrapper.h<br>+++ b/src/soc/amd/common/agesawrapper.h<br>@@ -51,7 +51,6 @@<br> <br> VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);<br> VOID amd_initcpuio(void);<br>-VOID amd_initmmio(void);<br> const void *agesawrapper_locate_module(const CHAR8 name[8]);<br> <br> void OemPostParams(AMD_POST_PARAMS *PostParams);<br>diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc<br>index 78ece2e..85452c4 100644<br>--- a/src/soc/amd/stoneyridge/Makefile.inc<br>+++ b/src/soc/amd/stoneyridge/Makefile.inc<br>@@ -39,7 +39,6 @@<br> <br> bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c<br> bootblock-y += BiosCallOuts.c<br>-bootblock-y += fixme.c<br> bootblock-y += bootblock/bootblock.c<br> bootblock-y += early_setup.c<br> bootblock-y += pmutil.c<br>@@ -50,7 +49,6 @@<br> romstage-y += early_setup.c<br> romstage-y += dimmSpd.c<br> romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c<br>-romstage-y += fixme.c<br> romstage-y += gpio.c<br> romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c<br> romstage-y += pmutil.c<br>@@ -73,7 +71,6 @@<br> ramstage-y += cpu.c<br> ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c<br> ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c<br>-ramstage-y += fixme.c<br> ramstage-y += gpio.c<br> ramstage-y += hda.c<br> ramstage-y += southbridge.c<br>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>index 1712b51..2c8d335 100644<br>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>@@ -17,11 +17,16 @@<br> #include <stdint.h><br> #include <assert.h><br> #include <console/console.h><br>+#include <cpu/x86/msr.h><br>+#include <cpu/x86/mtrr.h><br>+#include <cpu/amd/amdfam15.h><br> #include <smp/node.h><br> #include <bootblock_common.h><br> #include <agesawrapper.h><br> #include <agesawrapper_call.h><br> #include <soc/southbridge.h><br>+<br>+#define ROM_BASE ((uintptr_t)(0x100000000ull - CONFIG_ROM_SIZE))<br> <br> asmlinkage void bootblock_c_entry(uint64_t base_timestamp)<br> {<br>@@ -37,6 +42,26 @@<br> bootblock_main_with_timestamp(base_timestamp);<br> }<br> <br>+/* Set the MMIO Configuration Base Address and Bus Range. */<br>+static void amd_initmmio(void)<br>+{<br>+ msr_t mmconf;<br>+ msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);<br>+ int rom_mtrr;<br>+<br>+ mmconf.hi = 0;<br>+ mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN;<br>+ mmconf.lo |= (fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT);<br>+ wrmsr(MMIO_CONF_BASE, mmconf);<br>+<br>+ /*<br>+ * todo: AGESA currently writes variable MTRRs. Once that is<br>+ * corrected, un-hardcode this MTRR.<br>+ */<br>+ rom_mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2;<br>+ set_var_mtrr(rom_mtrr, ROM_BASE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);<br>+}<br>+<br> void bootblock_soc_early_init(void)<br> {<br> amd_initmmio();<br>diff --git a/src/soc/amd/stoneyridge/fixme.c b/src/soc/amd/stoneyridge/fixme.c<br>deleted file mode 100644<br>index 48344f1..0000000<br>--- a/src/soc/amd/stoneyridge/fixme.c<br>+++ /dev/null<br>@@ -1,81 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <device/device.h><br>-#include <cpu/cpu.h><br>-#include <cpu/x86/lapic_def.h><br>-#include <cpu/x86/msr.h><br>-#include <cpu/x86/mtrr.h><br>-#include <cpu/amd/mtrr.h><br>-#include <cpu/amd/amdfam15.h><br>-#include <soc/pci_devs.h><br>-#include <soc/pci_devs.h><br>-#include <soc/northbridge.h><br>-#include <soc/southbridge.h><br>-#include <agesawrapper.h><br>-<br>-#define ROM_BASE ((uintptr_t)(0x100000000ull - CONFIG_ROM_SIZE))<br>-<br>-/*<br>- * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,<br>- * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining<br>- * MMIO to posted. Route all I/O to the southbridge.<br>- */<br>-void amd_initcpuio(void)<br>-{<br>- msr_t topmem = rdmsr(TOP_MEM); /* todo: build bsp_topmem() earlier */<br>- u32 base, limit;<br>-<br>- /* Enable legacy video routing: D18F1xF4 VGA Enable */<br>- pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);<br>-<br>- /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */<br>- base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;<br>- limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;<br>- pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);<br>- pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);<br>-<br>- /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */<br>- base = (topmem.lo >> 8) | MMIO_WE | MMIO_RE;<br>- limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);<br>- pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO + 8, limit);<br>- pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO + 8, base);<br>-<br>- /* Send all I/O (0000-0xffff) to southbridge */<br>- base = 0 | MMIO_WE | MMIO_RE;<br>- limit = ALIGN_DOWN(0xffff, 4 * KiB);<br>- pci_write_config32(SOC_ADDR_DEV, D18F1_IO_LIMIT0, limit);<br>- pci_write_config32(SOC_ADDR_DEV, D18F1_IO_BASE0, base);<br>-}<br>-<br>-/* Set the MMIO Configuration Base Address and Bus Range. */<br>-void amd_initmmio(void)<br>-{<br>- msr_t mmconf;<br>- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);<br>- int rom_mtrr;<br>-<br>- mmconf.hi = 0;<br>- mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN;<br>- mmconf.lo |= (fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT);<br>- wrmsr(MMIO_CONF_BASE, mmconf);<br>-<br>- /*<br>- * todo: AGESA currently writes variable MTRRs. Once that is<br>- * corrected, un-hardcode this MTRR.<br>- */<br>- rom_mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2;<br>- set_var_mtrr(rom_mtrr, ROM_BASE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);<br>-}<br>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c<br>index 39001af..4716a10 100644<br>--- a/src/soc/amd/stoneyridge/northbridge.c<br>+++ b/src/soc/amd/stoneyridge/northbridge.c<br>@@ -22,6 +22,7 @@<br> #include <console/console.h><br> #include <cpu/amd/mtrr.h><br> #include <cpu/cpu.h><br>+#include <cpu/x86/lapic_def.h><br> #include <cpu/x86/msr.h><br> #include <device/device.h><br> #include <device/pci.h><br>@@ -29,6 +30,7 @@<br> #include <agesawrapper.h><br> #include <agesawrapper_call.h><br> #include <soc/northbridge.h><br>+#include <soc/southbridge.h><br> #include <soc/pci_devs.h><br> #include <stdint.h><br> #include <stdlib.h><br>@@ -334,6 +336,38 @@<br> .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT,<br> };<br> <br>+/*<br>+ * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,<br>+ * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining<br>+ * MMIO to posted. Route all I/O to the southbridge.<br>+ */<br>+void amd_initcpuio(void)<br>+{<br>+ u32 topmem = (u32)bsp_topmem();<br>+ u32 base, limit;<br>+<br>+ /* Enable legacy video routing: D18F1xF4 VGA Enable */<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);<br>+<br>+ /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */<br>+ base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;<br>+ limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);<br>+<br>+ /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */<br>+ base = (topmem >> 8) | MMIO_WE | MMIO_RE;<br>+ limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO + 8, limit);<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO + 8, base);<br>+<br>+ /* Send all I/O (0000-0xffff) to southbridge */<br>+ base = 0 | MMIO_WE | MMIO_RE;<br>+ limit = ALIGN_DOWN(0xffff, 4 * KiB);<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_IO_LIMIT0, limit);<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_IO_BASE0, base);<br>+}<br>+<br> void fam15_finalize(void *chip_info)<br> {<br> device_t dev;<br></pre><p>To view, visit <a href="https://review.coreboot.org/22297">change 22297</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22297"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3 </div>
<div style="display:none"> Gerrit-Change-Number: 22297 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>