[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add Intel common CPU code

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19540 )

Change subject: soc/intel/common/block: Add Intel common CPU code
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Patch Set 11:

(4 comments)

https://review.coreboot.org/#/c/19540/11/src/soc/intel/common/block/cpu/cpu.c
File src/soc/intel/common/block/cpu/cpu.c:

PS11, Line 124: #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
avoid #if use if (IS_ENABLED()) anyway you are having soft link


https://review.coreboot.org/#/c/19540/11/src/soc/intel/common/block/cpu/cpu_early.c
File src/soc/intel/common/block/cpu/cpu_early.c:

PS11, Line 106: set_pch_cpu_strap(nominal_ratio);
i guess this implementation differs between different socs.?


PS11, Line 316: ADDRESS + PM1_TMR);
> 80


https://review.coreboot.org/#/c/19540/11/src/soc/intel/common/block/include/intelblocks/msr.h
File src/soc/intel/common/block/include/intelblocks/msr.h:

PS11, Line 65: #define PRMRR_PHYS_BASE_MSR		0x1f4
don't keep this into common, it may be different between socs in future.


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Gerrit-MessageType: comment
Gerrit-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8
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