[coreboot-gerrit] Change in coreboot[master]: soc/broadwell: add missing USB port defs

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19968 )

Change subject: soc/broadwell: add missing USB port defs
......................................................................

soc/broadwell: add missing USB port defs

Add device/address stubs for XHCI USB ports 7/8, 10-15.
Stub data will be supplemented by board-specific info
added in subsequent commits.

Change-Id: Ice86bd226a70bd5996430e7a68a026cc825ba187
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/broadwell/acpi/xhci.asl
1 file changed, 8 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/19968/1

diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl
index a70ded9..bbf9878 100644
--- a/src/soc/intel/broadwell/acpi/xhci.asl
+++ b/src/soc/intel/broadwell/acpi/xhci.asl
@@ -362,5 +362,13 @@
 		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
 		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
 		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+		Device (PRT7) { Name (_ADR, 7) } // USB Port 6
+		Device (PRT8) { Name (_ADR, 8) } // USB Port 7
+		Device (SSP1) { Name (_ADR, 10) } // USB Port 10
+		Device (SSP2) { Name (_ADR, 11) } // USB Port 11
+		Device (SSP3) { Name (_ADR, 12) } // USB Port 12
+		Device (SSP4) { Name (_ADR, 13) } // USB Port 13
+		Device (SSP5) { Name (_ADR, 14) } // USB Port 14
+		Device (SSP6) { Name (_ADR, 15) } // USB Port 15
 	}
 }

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ice86bd226a70bd5996430e7a68a026cc825ba187
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>