[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: [WIP]Use CPU common code
Barnali Sarkar (Code Review)
gerrit at coreboot.org
Tue May 23 15:14:43 CEST 2017
Barnali Sarkar has uploaded a new change for review. ( https://review.coreboot.org/19827 )
Change subject: soc/intel/apollolake: [WIP]Use CPU common code
......................................................................
soc/intel/apollolake: [WIP]Use CPU common code
This patch uses common CPU Model library.
Change-Id: I529c67cf20253cf819d1c13849300788104b083c
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/include/soc/cpu.h
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/apollolake/tsc_freq.c
7 files changed, 17 insertions(+), 185 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/19827/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 56f0d20..8312611 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -54,6 +54,7 @@
select SOC_INTEL_COMMON_ACPI
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
+ select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_I2C
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 9b1f440..33bc7cf 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -94,6 +94,7 @@
verstage-y += reset.c
verstage-y += spi.c
+CPPFLAGS_common += -I$(src)/soc/intel/apollolake
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/apollolake
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 5211f84..10fbbf0 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -25,6 +25,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/cpu.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <intelblocks/itss.h>
@@ -44,6 +45,11 @@
static void *vbt;
static struct region_device vbt_rdev;
+
+void soc_fsp_load(void)
+{
+ fsps_load(romstage_handoff_is_resume());
+}
static const char *soc_acpi_name(struct device *dev)
{
@@ -147,7 +153,7 @@
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
- .init = apollolake_init_cpus,
+ .init = DEVICE_NOOP,
.scan_bus = NULL,
.acpi_fill_ssdt_generator = generate_cpu_entries,
};
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index ff300bc..8b7c202 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -53,14 +53,7 @@
REG_SCRIPT_END
};
-void enable_untrusted_mode(void)
-{
- msr_t msr = rdmsr(MSR_POWER_MISC);
- msr.lo |= ENABLE_IA_UNTRUSTED;
- wrmsr(MSR_POWER_MISC, msr);
-}
-
-static void soc_core_init(device_t cpu)
+void cpu_core_init(device_t cpu)
{
/* Set core MSRs */
reg_script_run(core_msr_script);
@@ -72,138 +65,8 @@
enable_pm_timer_emulation();
}
-static struct device_operations cpu_dev_ops = {
- .init = soc_core_init,
-};
-
-static struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 },
- { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 },
- { 0, 0 },
-};
-
-static const struct cpu_driver driver __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
-};
-
-/*
- * MP and SMM loading initialization.
- */
-struct smm_relocation_attrs {
- uint32_t smbase;
- uint32_t smrr_base;
- uint32_t smrr_mask;
-};
-
-static struct smm_relocation_attrs relo_attrs;
-
-static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
+void soc_init_cpus(void)
{
- msr_t msr;
- msr = rdmsr(MSR_CORE_THREAD_COUNT);
- *num_virt = (msr.lo >> 0) & 0xffff;
- *num_phys = (msr.lo >> 16) & 0xffff;
-}
-
-/*
- * Do essential initialization tasks before APs can be fired up
- *
- * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
- * creates the MTRR solution that the APs will use. Otherwise APs will try to
- * apply the incomplete solution as the BSP is calculating it.
- */
-static void pre_mp_init(void)
-{
- x86_setup_mtrrs_with_detect();
- x86_mtrr_check();
-
- /* Make sure BSP is using the microcode from cbfs */
- intel_update_microcode_from_cbfs();
-}
-
-/* Find CPU topology */
-static int get_cpu_count(void)
-{
- unsigned int num_virt_cores, num_phys_cores;
-
- read_cpu_topology(&num_phys_cores, &num_virt_cores);
-
- printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n",
- num_phys_cores, num_virt_cores);
-
- return num_virt_cores;
-}
-
-static void get_microcode_info(const void **microcode, int *parallel)
-{
- *microcode = intel_microcode_find();
- *parallel = 1;
-}
-
-static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
- size_t *smm_save_state_size)
-{
- void *smm_base;
- size_t smm_size;
- void *handler_base;
- size_t handler_size;
-
- /* All range registers are aligned to 4KiB */
- const uint32_t rmask = ~((1 << 12) - 1);
-
- /* Initialize global tracking state. */
- smm_region(&smm_base, &smm_size);
- smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-
- relo_attrs.smbase = (uint32_t)smm_base;
- relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
- relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
- relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
-
- *perm_smbase = (uintptr_t)handler_base;
- *perm_smsize = handler_size;
- *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
-}
-
-static void relocation_handler(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase)
-{
- msr_t smrr;
- em64t100_smm_state_save_area_t *smm_state;
- /* Set up SMRR. */
- smrr.lo = relo_attrs.smrr_base;
- smrr.hi = 0;
- wrmsr(SMRR_PHYS_BASE, smrr);
- smrr.lo = relo_attrs.smrr_mask;
- smrr.hi = 0;
- wrmsr(SMRR_PHYS_MASK, smrr);
- smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
- smm_state->smbase = staggered_smbase;
-}
-/*
- * CPU initialization recipe
- *
- * Note that no microcode update is passed to the init function. CSE updates
- * the microcode on all cores before releasing them from reset. That means that
- * the BSP and all APs will come up with the same microcode revision.
- */
-static const struct mp_ops mp_ops = {
- .pre_mp_init = pre_mp_init,
- .get_cpu_count = get_cpu_count,
- .get_smm_info = get_smm_info,
- .get_microcode_info = get_microcode_info,
- .pre_mp_smm_init = southbridge_smm_clear_state,
- .relocation_handler = relocation_handler,
- .post_mp_init = southbridge_smm_enable_smi,
-};
-
-void apollolake_init_cpus(device_t dev)
-{
- /* Clear for take-off */
- if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)
- printk(BIOS_ERR, "MP initialization failure.\n");
-
/* Temporarily cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
mtrr_use_temp_range(-CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 3391597..ec7b94b 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -21,16 +21,14 @@
#include <intelblocks/msr.h>
#ifndef __ASSEMBLER__
+#include <arch/io.h>
+#include <chip.h>
#include <cpu/x86/msr.h>
#include <device/device.h>
-void apollolake_init_cpus(struct device *dev);
-void set_max_freq(void);
-void enable_untrusted_mode(void);
+void cpu_core_init(device_t cpu);
+void soc_init_cpus(void);
#endif
-
-#define CPUID_APOLLOLAKE_A0 0x506c8
-#define CPUID_APOLLOLAKE_B0 0x506c9
#define BASE_CLOCK_MHZ 100
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 39d3989..f6ac401 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -31,6 +31,7 @@
#include <fsp/api.h>
#include <fsp/memmap.h>
#include <fsp/util.h>
+#include <intelblocks/cpu.h>
#include <reset.h>
#include <soc/cpu.h>
#include <soc/intel/common/mrc_cache.h>
diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
index f91a047..db456bf 100644
--- a/src/soc/intel/apollolake/tsc_freq.c
+++ b/src/soc/intel/apollolake/tsc_freq.c
@@ -27,42 +27,4 @@
{
msr_t msr = rdmsr(MSR_PLATFORM_INFO);
return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
-}
-
-void set_max_freq(void)
-{
- msr_t msr, msr_rd;
- unsigned int eax;
-
- eax = cpuid_eax(CPUID_LEAF_PM);
-
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
- eax &= 0x2;
- if ((!eax) && ((msr.hi & APL_BURST_MODE_DISABLE) == 0)) {
- /* Burst Mode has been factory configured as disabled
- * and is not available in this physical processor
- * package.
- */
- printk(BIOS_DEBUG, "Burst Mode is factory disabled\n");
- return;
- }
-
- /* Enable burst mode */
- msr.hi &= ~APL_BURST_MODE_DISABLE;
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
-
- /* Enable speed step. */
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
- msr.lo |= 1 << 16;
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
-
- /* Set P-State ratio */
- msr = rdmsr(IA32_PERF_CTL);
- msr.lo &= ~0xff00;
-
- /* Read the frequency limit ratio and set it properly in PERF_CTL */
- msr_rd = rdmsr(FREQ_LIMIT_RATIO);
- msr.lo |= (msr_rd.lo & 0xff) << 8;
-
- wrmsr(IA32_PERF_CTL, msr);
-}
+}
\ No newline at end of file
--
To view, visit https://review.coreboot.org/19827
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I529c67cf20253cf819d1c13849300788104b083c
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
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