[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR

[Patrick Rudolph (Code Review)]

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/19543 )

Change subject: sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR
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sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR

Lock CF9GR as documented in "100-series-chipset-datasheet-vol-2.pdf"

Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
Reviewed-on: https://review.coreboot.org/19543
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h at gmx.de>
---
M src/southbridge/intel/bd82x6x/finalize.c
M src/southbridge/intel/bd82x6x/pch.h
2 files changed, 4 insertions(+), 0 deletions(-)

Approvals:
  Paul Menzel: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved



diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index 4e08fc6..9c453e4 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -65,6 +65,9 @@
 	/* GEN_PMCON Lock */
 	pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2));
 
+	/* ETR3: CF9GR Lockdown */
+	pci_update_config32(PCH_LPC_DEV, ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK);
+
 	/* R/WO registers */
 	RCBA32(0x21a4) = RCBA32(0x21a4);
 	pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index da1f901..f8131da 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -144,6 +144,7 @@
 #define ETR3			0xac
 #define  ETR3_CWORWRE		(1 << 18)
 #define  ETR3_CF9GR		(1 << 20)
+#define  ETR3_CF9LOCK		(1 << 31)
 
 /* GEN_PMCON_3 bits */
 #define RTC_BATTERY_DEAD	(1 << 2)

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>