[coreboot-gerrit] Change in coreboot[master]: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob

[Caesar Wang (Code Review)]

Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19557 )

Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
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Patch Set 4:

(1 comment)

https://review.coreboot.org/#/c/19557/4/src/soc/rockchip/rk3399/clock.c
File src/soc/rockchip/rk3399/clock.c:

PS4, Line 359: /* Wait for the dpll stable */
             : 	udelay(30);
             : 	assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6);
Can we change it with the below patch?

+       if (!(dpll_cfg->refdiv && dpll_cfg->refdiv <=6)) {
+               printk(BIOS_ERR,"%s: failed to get refdiv(%d)\n",__func__,
+                      dpll_cfg->refdiv);
+               return;
+       }
That's fine from the short test. I don't see the error log.


That's weird, we should printf the log if the assert() failed.


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Gerrit-MessageType: comment
Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Caesar Wang <wxt at rock-chips.com>
Gerrit-Reviewer: Caesar Wang <wxt at rock-chips.com>
Gerrit-Reviewer: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Philip Chen <philipchen at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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