[coreboot-gerrit] Change in coreboot[master]: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob

[Caesar Wang (Code Review)]

Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19557 )

Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
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Patch Set 4:

(2 comments)

https://review.coreboot.org/#/c/19557/4/src/soc/rockchip/rk3399/clock.c
File src/soc/rockchip/rk3399/clock.c:

Line 360: 	udelay(30);
> Is this delay needed? There's nothing coming before here? If it's still in 
>From the actual test, we need 10us delay at least.
Yes, we need find the root cause, but I believe it's no related to enable the SSC  

The other way we cat put the rkclk_set_dpllssc() into src/soc/rockchip/rk3399/sdram.c or src/mainboard/google/gru/romstage.c to enable later


Line 373: 			      PLL_FRAC_MODE << PLL_DSMPD_SHIFT));
> So we're enabling fractional mode here, but where are we setting the fracti
I　believe this fractional mode is different with the pll fractional divider.

The pll fractional divider is configured by the other interface.


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Gerrit-MessageType: comment
Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Caesar Wang <wxt at rock-chips.com>
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