[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add Intel XDCI code support

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19428 )

Change subject: soc/intel/common/block: Add Intel XDCI code support
......................................................................


soc/intel/common/block: Add Intel XDCI code support

XDCI MMIO offsets definitions are not alike between
various SoCs hence provided "soc_xdci_init" function
to implement SoC specific initialization.

Change-Id: I9cbc686a00c26b92be2847b6bd6c2e5aa5a690f7
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
Reviewed-on: https://review.coreboot.org/19428
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
A src/soc/intel/common/block/include/intelblocks/xdci.h
A src/soc/intel/common/block/xdci/Kconfig
A src/soc/intel/common/block/xdci/Makefile.inc
A src/soc/intel/common/block/xdci/xdci.c
4 files changed, 69 insertions(+), 0 deletions(-)

Approvals:
  Aaron Durbin: Looks good to me, approved
  build bot (Jenkins): Verified



diff --git a/src/soc/intel/common/block/include/intelblocks/xdci.h b/src/soc/intel/common/block/include/intelblocks/xdci.h
new file mode 100644
index 0000000..fa25513
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/xdci.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_XDCI_H
+#define SOC_INTEL_COMMON_BLOCK_XDCI_H
+
+void soc_xdci_init(struct device *dev);
+
+#endif	/* SOC_INTEL_COMMON_BLOCK_XDCI_H */
diff --git a/src/soc/intel/common/block/xdci/Kconfig b/src/soc/intel/common/block/xdci/Kconfig
new file mode 100644
index 0000000..3918642
--- /dev/null
+++ b/src/soc/intel/common/block/xdci/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_XDCI
+	bool
+	help
+	  Intel Processor common XDCI support
diff --git a/src/soc/intel/common/block/xdci/Makefile.inc b/src/soc/intel/common/block/xdci/Makefile.inc
new file mode 100644
index 0000000..3326cde
--- /dev/null
+++ b/src/soc/intel/common/block/xdci/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI) += xdci.c
diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c
new file mode 100644
index 0000000..c9cc632
--- /dev/null
+++ b/src/soc/intel/common/block/xdci/xdci.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <intelblocks/xdci.h>
+
+__attribute__((weak)) void soc_xdci_init(struct device *dev) { /* no-op */ }
+
+static struct device_operations usb_xdci_ops = {
+	.read_resources		= &pci_dev_read_resources,
+	.set_resources		= &pci_dev_set_resources,
+	.enable_resources	= &pci_dev_enable_resources,
+	.init			= soc_xdci_init,
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DEVICE_ID_INTEL_APOLLOLAKE_XDCI,
+	PCI_DEVICE_ID_INTEL_GLK_XDCI,
+	PCI_DEVICE_ID_INTEL_SPT_LP_XDCI,
+	0
+};
+
+static const struct pci_driver pch_usb_xdci __pci_driver = {
+	.ops	 = &usb_xdci_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices	 = pci_device_ids,
+};

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: I9cbc686a00c26b92be2847b6bd6c2e5aa5a690f7
Gerrit-PatchSet: 6
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Andrey Petrov <andrey.petrov at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: V Sowmya <v.sowmya at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>