[coreboot-gerrit] Change in coreboot[master]: mb/*/romstage: Don't lock ETR3 CF9GR in early romstage
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Thu May 4 19:14:38 CEST 2017
Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19570 )
Change subject: mb/*/romstage: Don't lock ETR3 CF9GR in early romstage
......................................................................
mb/*/romstage: Don't lock ETR3 CF9GR in early romstage
Do not lock ETR3 CF9GR in early romstage.
As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done
in bd82x6x's finalize handler.
Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
M src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
M src/mainboard/lenovo/l520/romstage.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/lenovo/t420/romstage.c
M src/mainboard/lenovo/t420s/romstage.c
M src/mainboard/lenovo/t430s/romstage.c
M src/mainboard/lenovo/t520/romstage.c
M src/mainboard/lenovo/t530/romstage.c
M src/mainboard/lenovo/x1_carbon_gen1/romstage.c
M src/mainboard/lenovo/x220/romstage.c
M src/mainboard/lenovo/x230/romstage.c
12 files changed, 11 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/19570/1
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index bb3b223..cbc5592 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -153,7 +153,7 @@
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
index 4a02790..22a10ae 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -85,7 +85,7 @@
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c
index 47b9fd6..6c93eed 100644
--- a/src/mainboard/lenovo/l520/romstage.c
+++ b/src/mainboard/lenovo/l520/romstage.c
@@ -31,7 +31,6 @@
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
index ad5f021..610eb89 100644
--- a/src/mainboard/lenovo/s230u/romstage.c
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -43,7 +43,7 @@
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000);
/* Memory map KB9012 EC registers */
pci_write_config32(
diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c
index d25ce45..766b019 100644
--- a/src/mainboard/lenovo/t420/romstage.c
+++ b/src/mainboard/lenovo/t420/romstage.c
@@ -33,7 +33,7 @@
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c
index 27b45fd..e32337a 100644
--- a/src/mainboard/lenovo/t420s/romstage.c
+++ b/src/mainboard/lenovo/t420s/romstage.c
@@ -36,7 +36,7 @@
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c
index 92f9e62..a17ec52 100644
--- a/src/mainboard/lenovo/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/romstage.c
@@ -36,7 +36,7 @@
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 5ba4873..fd17f21 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -50,8 +50,7 @@
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac,
- 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index 3d603c5..050e8cf 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -37,8 +37,7 @@
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac,
- 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
index 3e11324..574d02b 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
@@ -51,8 +51,7 @@
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac,
- 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 5a1c90a..15d2c84 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -47,8 +47,7 @@
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac,
- 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 53ad9ac..e68843c 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -50,8 +50,7 @@
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac,
- 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)
--
To view, visit https://review.coreboot.org/19570
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
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