[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add PCI configuration code for UART
Aamir Bohra (Code Review)
gerrit at coreboot.org
Tue May 2 12:47:26 CEST 2017
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/19490 )
Change subject: soc/intel/common: Add PCI configuration code for UART
......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/#/c/19490/1/src/soc/intel/common/block/uart/uart.c
File src/soc/intel/common/block/uart/uart.c:
Line 23: uint32_t clk_n_val)
> You can't have this be a nop. It won't read *any* resources. It needs to ca
Ok.Revised implementation in PS#2
PS1, Line 56: /*
> space after '*'
Done
PS1, Line 56: 0xa127, /* KBL-H UART0 */
: 0xa128, /* KBL-H UART1 */
: 0xa166, /* KBL-H UART2 */
: 0x5abc, /* Apollolake UART0 */
: 0x5abe, /* Apollolake UART1 */
: 0x5ac0, /* Apollolake UART2 */
: 0x5aee, /* Apollolake UART3 */
: 0x31bc, /* GLK UART0 */
: 0x31be, /* GLK UART1 */
: 0x31c0, /* GLK UART2 */
: 0x31ee, /* GLK UART3 */
: };
:
: static const struct pci_
> These should be put into pci_ids.h then.
Ok.Do you suggest to move it to soc/pci_ids.h or define it under common?
Line 75
> seems like tabs and spaces are being mixed between .field and =
Done
--
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Gerrit-MessageType: comment
Gerrit-Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)
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