[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add cache as ram init and teardown code

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18381 )

Change subject: soc/intel/common/block: Add cache as ram init and teardown code
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Patch Set 33:

(3 comments)

https://review.coreboot.org/#/c/18381/33/src/soc/intel/common/block/cpu/car/cache_as_ram.S
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

Line 113: #if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0)
> This condition is in the wrong place. It needs to be above the PHYS_BASE(0)
I was earlier written this code with an assumption that there could be 3 condition.
1. We are passing DCACHE_RAM_SIZE which is power of 2 and !768KB
2. DCACHE_RAM_SIZE == 768KB
3. DCACHE_RAM_SIZE != Power of 2

In #1 and #2 we should program BASE(0) unconditionally and for MASK(0)/BASE(1)/MASK(1) we need to apply some conditional operation hence added those inside #if logic and take BASE(0) program at common place.

Flaw in my logic was in case of #3 also, i will end up doing BASE(0) programming but any any way guard with #error so, we will not face any runtime issue. its just a compilation check.

By all mean i think taking BASE(0) out of any such #if or #elseif is okay, i don;t see any mistake there. is that i'm missing anything?


Line 133: 
> You are missing PHYS_MASK(0) programming here. Also, remember to include es
I don't understand when you say "missing PHY_MASK(0) programming here". as i mentioned above for #1 condition we have PHYS_MASK(0) programming between line 114-121 (this also address esi there)

For #2, PHYS_MASK(0) is in line 123-126, but there are 2 problem. first, programming not same between those two PHYS_MASK(0), in one case i have used x86 instruction and other case use compiler. Second, esi is missing there.

did u mean the same? i guess i have analysis this code few time before making those common, i'm missing anything?


https://review.coreboot.org/#/c/18381/33/src/soc/intel/skylake/Kconfig
File src/soc/intel/skylake/Kconfig:

PS33, Line 188: config SOC_INTEL_COMMON_BLOCK_CAR
              : 	bool
              : 	default y if !FSP_CAR
              : 	select INTEL_CAR_NEM_ENHANCED
mistake, will remove this


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Gerrit-MessageType: comment
Gerrit-Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Gerrit-PatchSet: 33
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>
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