[coreboot-gerrit] Change in coreboot[master]: nb/intel/i945: Fix errors found by checkpatch.pl
Martin Roth (Code Review)
gerrit at coreboot.org
Wed Mar 22 17:55:43 CET 2017
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18704 )
Change subject: nb/intel/i945: Fix errors found by checkpatch.pl
......................................................................
nb/intel/i945: Fix errors found by checkpatch.pl
Change-Id: Ic2dd40e73d4a4c091c5ce1f49bbf9ab4d013d7af
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18704
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth at google.com>
---
M src/northbridge/intel/i945/acpi.c
M src/northbridge/intel/i945/bootblock.c
M src/northbridge/intel/i945/debug.c
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/i945.h
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/i945/ram_calc.c
M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/i945/rcven.c
M src/northbridge/intel/i945/udelay.c
11 files changed, 450 insertions(+), 400 deletions(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c
index 71694c8..c1a3d17 100644
--- a/src/northbridge/intel/i945/acpi.c
+++ b/src/northbridge/intel/i945/acpi.c
@@ -34,7 +34,7 @@
u32 pciexbar_reg;
int max_buses;
- dev = dev_find_slot(0, PCI_DEVFN(0,0));
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev)
return current;
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index d837122..4c3c90c 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -20,5 +20,5 @@
* 4GiB.
*/
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
- pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
+ pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);
}
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index 4804544..acf73c4 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -26,7 +26,7 @@
pci_devfn_t dev;
for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
+ dev += PCI_DEV(0, 0, 1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
@@ -36,11 +36,11 @@
}
printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
(dev >> 15) & 0x1f, (dev >> 12) & 7);
- printk(BIOS_DEBUG, " [%04x:%04x]\n", id &0xffff, id >> 16);
+ printk(BIOS_DEBUG, " [%04x:%04x]\n", id & 0xffff, id >> 16);
}
}
-void dump_pci_device(unsigned dev)
+void dump_pci_device(unsigned int dev)
{
int i;
@@ -48,14 +48,12 @@
for (i = 0; i <= 255; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
- }
val = pci_read_config8(dev, i);
printk(BIOS_DEBUG, " %02x", val);
- if ((i & 0x0f) == 0x0f) {
+ if ((i & 0x0f) == 0x0f)
printk(BIOS_DEBUG, "\n");
- }
}
}
@@ -64,7 +62,7 @@
pci_devfn_t dev;
for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
+ dev += PCI_DEV(0, 0, 1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
@@ -78,7 +76,7 @@
void dump_spd_registers(void)
{
- unsigned device;
+ unsigned int device;
device = DIMM0;
while (device <= DIMM3) {
int status = 0;
@@ -86,14 +84,12 @@
printk(BIOS_DEBUG, "\ndimm %02x", device);
for (i = 0; (i < 256); i++) {
- if ((i % 16) == 0) {
+ if ((i % 16) == 0)
printk(BIOS_DEBUG, "\n%02x: ", i);
- }
status = smbus_read_byte(device, i);
- if (status < 0) {
+ if (status < 0)
printk(BIOS_DEBUG, "bad device: %02x\n", -status);
break;
- }
printk(BIOS_DEBUG, "%02x ", status);
}
device++;
@@ -101,14 +97,13 @@
}
}
-void dump_mem(unsigned start, unsigned end)
+void dump_mem(unsigned int start, unsigned int end)
{
- unsigned i;
+ unsigned int i;
printk(BIOS_DEBUG, "dump_mem:");
for (i = start; i < end; i++) {
- if ((i & 0xf)==0) {
+ if ((i & 0xf) == 0)
printk(BIOS_DEBUG, "\n%08x:", i);
- }
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
}
printk(BIOS_DEBUG, "\n");
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 81a6c83..0a2c99e 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -160,10 +160,10 @@
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */
setup_pch_gpios(&mainboard_gpio_map);
printk(BIOS_DEBUG, " done.\n");
@@ -253,7 +253,7 @@
EPBAR32(EPVC1RCAP) = reg32;
if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
- if ((MCHBAR32(CLKCFG) & 7) == 0){ /* 1067MHz */
+ if ((MCHBAR32(CLKCFG) & 7) == 0) { /* 1067MHz */
EPBAR32(EPVC1IST + 0) = 0x01380138;
EPBAR32(EPVC1IST + 4) = 0x01380138;
}
@@ -275,9 +275,8 @@
}
/* Is internal graphics enabled? */
- if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
+ if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
MCHBAR32(MMARB1) |= (1 << 17);
- }
/* Assign Virtual Channel ID 1 to VC1 */
reg32 = EPBAR32(EPVC1RCTL);
@@ -305,7 +304,8 @@
printk(BIOS_DEBUG, "Loading port arbitration table ...");
/* Loop until bit 0 becomes 0 */
timeout = 0x7fffff;
- while ((EPBAR16(EPVC1RSTS) & 1) && --timeout);
+ while ((EPBAR16(EPVC1RSTS) & 1) && --timeout)
+ ;
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
else
@@ -317,7 +317,8 @@
printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
/* Wait for VC1 negotiation pending */
timeout = 0x7fff;
- while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout);
+ while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout)
+ ;
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
else
@@ -355,7 +356,7 @@
pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0);
reg32 = RCBA32(V1CTL);
- reg32 &= ~( (0x7f << 1) | (7 << 17) | (7 << 24) );
+ reg32 &= ~((0x7f << 1) | (7 << 17) | (7 << 24));
reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31);
RCBA32(V1CTL) = reg32;
@@ -410,7 +411,8 @@
printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
/* Wait for VC1 negotiation pending */
timeout = 0x7ffff;
- while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout);
+ while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout)
+ ;
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
else
@@ -436,9 +438,8 @@
DMIBAR32(DMICC) = reg32;
- if (activate_aspm) {
+ if (activate_aspm)
DMIBAR32(DMILCTL) |= (3 << 0);
- }
#endif
/* Last but not least, some additional steps */
@@ -510,7 +511,8 @@
/* wait for bit toggle to 0 */
printk(BIOS_DEBUG, "Waiting for DMI hardware...");
timeout = 0x7fffff;
- while ((DMIBAR8(0x32) & (1 << 1)) && --timeout);
+ while ((DMIBAR8(0x32) & (1 << 1)) && --timeout)
+ ;
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
else
@@ -576,9 +578,8 @@
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
- if (!(reg16 & 0x48)) {
+ if (!(reg16 & 0x48))
goto disable_pciexpress_x16_link;
- }
reg16 |= (1 << 4) | (1 << 0);
pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16);
@@ -591,7 +592,7 @@
reg32 &= ~(1 << 8);
pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
- MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) );
+ MCHBAR16(UPMC1) &= ~((1 << 5) | (1 << 0));
/* Initialize PEG_CAP */
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xa2);
@@ -613,7 +614,9 @@
/* Wait for training to succeed */
printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff;
- while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout);
+ while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)
+ && --timeout)
+ ;
reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
@@ -626,7 +629,7 @@
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS);
reg32 &= ~(0xf << 1);
- reg32 |=1;
+ reg32 |= 1;
pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
@@ -638,7 +641,9 @@
printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff;
- while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout);
+ while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)
+ && --timeout)
+ ;
reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
@@ -659,15 +664,14 @@
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x204);
reg32 &= 0xfffffc00; /* clear [9:0] */
- if (reg16 == 1) {
+ if (reg16 == 1)
reg32 |= 0x32b;
// TODO
/* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
- } else if (reg16 == 16) {
+ else if (reg16 == 16)
reg32 |= 0x0f4;
// TODO
/* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
- }
reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32);
@@ -749,11 +753,10 @@
pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32);
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
- if (i945_silicon_revision() >= 2) {
+ if (i945_silicon_revision() >= 2)
reg32 |= (1 << 12);
- } else {
+ else
reg32 &= ~(1 << 12);
- }
pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4);
@@ -780,7 +783,7 @@
}
}
- if (i945_silicon_revision() <= 2 ) {
+ if (i945_silicon_revision() <= 2) {
/* Set voltage specific parameters */
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
reg32 &= (0xf << 4); /* Default case 1.05V */
@@ -813,7 +816,8 @@
printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
timeout = 0x7fffff;
for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS);
- (reg32 & 0x000f0000) && --timeout;);
+ (reg32 & 0x000f0000) && --timeout;)
+ ;
if (!timeout)
printk(BIOS_DEBUG, "timeout!\n");
else
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index e3fe097..0765767 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -193,7 +193,7 @@
}
if (smallest_err == 0xffffffff) {
- printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n");
return -1;
}
@@ -314,14 +314,14 @@
write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS
| PANEL_POWER_ON | PANEL_POWER_RESET);
- printk (BIOS_DEBUG, "waiting for panel powerup\n");
+ printk(BIOS_DEBUG, "waiting for panel powerup\n");
while (1) {
u32 reg32;
reg32 = read32(mmiobase + PP_STATUS);
if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE)
break;
}
- printk (BIOS_DEBUG, "panel powered up\n");
+ printk(BIOS_DEBUG, "panel powered up\n");
write32(mmiobase + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
@@ -346,8 +346,7 @@
printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
}
- for (i = 0; i < (uma_size - 256) / 4; i++)
- {
+ for (i = 0; i < (uma_size - 256) / 4; i++) {
outl((i << 2) | 1, piobase);
outl(pphysbase + (i << 12) + 1, piobase + 4);
}
@@ -486,7 +485,7 @@
write32(mmiobase + PF_WIN_POS(0), 0);
write32(mmiobase + PIPESRC(0), (639 << 16) | 399);
- write32(mmiobase + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
+ write32(mmiobase + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
write32(mmiobase + PF_WIN_SZ(0), vactive | (hactive << 16));
write32(mmiobase + PFIT_CONTROL, 0x0);
@@ -526,8 +525,7 @@
printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
}
- for (i = 0; i < (uma_size - 256) / 4; i++)
- {
+ for (i = 0; i < (uma_size - 256) / 4; i++) {
outl((i << 2) | 1, piobase);
outl(pphysbase + (i << 12) + 1, piobase + 4);
}
@@ -634,7 +632,8 @@
udelay(50);
pci_write_config8(dev, GDRST, 0);
/* wait for device to finish */
- while (pci_read_config8(dev, GDRST) & 1) { };
+ while (pci_read_config8(dev, GDRST) & 1)
+ ;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
@@ -721,7 +720,8 @@
pci_write_config8(dev, 0xf4, 0xff);
}
-static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void gma_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -735,23 +735,20 @@
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
- if (!dev) {
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
+ if (!dev)
return NULL;
- }
struct northbridge_intel_i945_config *chip = dev->chip_info;
- if (!chip) {
+ if (!chip)
return NULL;
- }
return &chip->gfx;
}
static void gma_ssdt(device_t device)
{
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
- if (!gfx) {
+ if (!gfx)
return;
- }
drivers_intel_gma_displays_ssdt_generate(gfx);
}
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 1686acc..330ace1 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -61,7 +61,7 @@
#define DEVEN_D2F1 (1 << 4)
#ifndef BOARD_DEVEN
-#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 )
+#define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1)
#endif /* BOARD_DEVEN */
#define PAM0 0x90
@@ -99,9 +99,9 @@
* MCHBAR
*/
-#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
-#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
-#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
+#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
+#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
/* Chipset Control Registers */
#define FSBPMC3 0x40 /* 32bit */
@@ -283,9 +283,9 @@
* EPBAR - Egress Port Root Complex Register Block
*/
-#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
-#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
-#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
+#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x))))
+#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
+#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
#define EPPVCCAP1 0x004 /* 32bit */
#define EPPVCCAP2 0x008 /* 32bit */
@@ -314,9 +314,9 @@
* DMIBAR
*/
-#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
-#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
-#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x))))
+#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
+#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
#define DMIVCECH 0x000 /* 32bit */
#define DMIPVCCAP1 0x004 /* 32bit */
@@ -359,10 +359,10 @@
/* debugging functions */
void print_pci_devices(void);
-void dump_pci_device(unsigned dev);
+void dump_pci_device(unsigned int dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
-void dump_mem(unsigned start, unsigned end);
+void dump_mem(unsigned int start, unsigned int end);
u32 decode_igd_memory_size(u32 gms);
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index f6c3364..57f4388 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -163,7 +163,8 @@
}
}
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void intel_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -214,11 +215,10 @@
static void enable_dev(device_t dev)
{
/* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
dev->ops = &pci_domain_ops;
- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &cpu_bus_ops;
- }
}
struct chip_operations northbridge_intel_i945_ops = {
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index a8ef065..0c337bb 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -29,15 +29,14 @@
{
uintptr_t tom;
- if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
+ if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
/* IGD enabled, get top of Memory from BSM register */
- tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
- } else {
- tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
- }
+ tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM);
+ else
+ tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24;
/* if TSEG enabled subtract size */
- switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
+ switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
case 0x01:
/* 1MB TSEG */
tom -= 0x100000;
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index b5cce9c..0499b48 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -60,7 +60,7 @@
}
-static inline int spd_read_byte(unsigned device, unsigned address)
+static inline int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
@@ -70,7 +70,7 @@
u32 reg32;
reg32 = MCHBAR32(DCC);
- reg32 &= ~( (3<<21) | (1<<20) | (1<<19) | (7 << 16) );
+ reg32 &= ~((3<<21) | (1<<20) | (1<<19) | (7 << 16));
reg32 |= command;
/* Also set Init Complete */
@@ -99,7 +99,7 @@
int i;
printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
- for (i = 0; i < 0xfff; i+=4) {
+ for (i = 0; i < 0xfff; i += 4) {
if (MCHBAR32(i) == 0)
continue;
printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
@@ -115,7 +115,9 @@
case 1: return 400;
case 2: return 533;
case 3: return 667;
- default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
+ default:
+ printk(BIOS_DEBUG, "memclk: unknown register value %x\n",
+ ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
}
return -1;
}
@@ -127,7 +129,9 @@
case 0: return 400;
case 1: return 533;
case 3: return 667;
- default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
+ default:
+ printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n",
+ MCHBAR32(CLKCFG) & 7);
}
return 0xffff;
} else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
@@ -135,7 +139,9 @@
case 0: return 1066;
case 1: return 533;
case 2: return 800;
- default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
+ default:
+ printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n",
+ MCHBAR32(CLKCFG) & 7);
}
return 0xffff;
}
@@ -173,7 +179,7 @@
{
u32 reg32;
- reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
+ reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
reg32 >>= 25;
reg32 &= 1;
@@ -189,7 +195,7 @@
{
u32 reg32;
- reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
+ reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
reg32 >>= 24;
reg32 &= 1;
@@ -232,7 +238,7 @@
reg8 &= (1 << 3) | (1 << 2) | (1 << 1);
reg8 >>= 1;
- return (reg8);
+ return reg8;
}
static void sdram_detect_errors(struct sys_info *sysinfo)
@@ -357,7 +363,7 @@
*
*/
- for (i = 0; i<(2 * DIMM_SOCKETS); i++) {
+ for (i = 0; i < (2 * DIMM_SOCKETS); i++) {
int device = get_dimm_spd_address(sysinfo, i);
u8 reg8;
@@ -421,13 +427,11 @@
dimm_mask |= (1 << i);
}
- if (!dimm_mask) {
+ if (!dimm_mask)
die("No memory installed.\n");
- }
- if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
+ if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1)))
printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
- }
}
/**
@@ -435,7 +439,7 @@
*
* @param sysinfo central sysinfo data structure.
*/
-static void sdram_verify_package_type(struct sys_info * sysinfo)
+static void sdram_verify_package_type(struct sys_info *sysinfo)
{
int i;
@@ -451,7 +455,7 @@
}
}
-static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
+static u8 sdram_possible_cas_latencies(struct sys_info *sysinfo)
{
int i;
u8 cas_mask;
@@ -467,14 +471,13 @@
SPD_ACCEPTABLE_CAS_LATENCIES);
}
- if (!cas_mask) {
+ if (!cas_mask)
die("No DDR-II modules with accepted CAS latencies found.\n");
- }
return cas_mask;
}
-static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask)
+static void sdram_detect_cas_latency_and_ram_speed(struct sys_info *sysinfo, u8 cas_mask)
{
int i, j, idx;
int lowest_common_cas = 0;
@@ -493,59 +496,58 @@
};
switch (sdram_capabilities_max_supported_memory_frequency()) {
- case 400: max_ram_speed = 0; break;
- case 533: max_ram_speed = 1; break;
- case 667: max_ram_speed = 2; break;
+ case 400:
+ max_ram_speed = 0; break;
+ case 533:
+ max_ram_speed = 1; break;
+ case 667:
+ max_ram_speed = 2; break;
}
sysinfo->memory_frequency = 0;
sysinfo->cas = 0;
- if (cas_mask & SPD_CAS_LATENCY_DDR2_3) {
+ if (cas_mask & SPD_CAS_LATENCY_DDR2_3)
lowest_common_cas = 3;
- } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) {
+ else if (cas_mask & SPD_CAS_LATENCY_DDR2_4)
lowest_common_cas = 4;
- } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) {
+ else if (cas_mask & SPD_CAS_LATENCY_DDR2_5)
lowest_common_cas = 5;
- }
PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas);
- for (j = max_ram_speed; j>=0; j--) {
+ for (j = max_ram_speed; j >= 0; j--) {
int freq_cas_mask = cas_mask;
PRINTK_DEBUG("Probing Speed %d\n", j);
- for (i = 0; i < 2*DIMM_SOCKETS; i++) {
+ for (i = 0; i < 2 * DIMM_SOCKETS; i++) {
int device = get_dimm_spd_address(sysinfo, i);
int current_cas_mask;
PRINTK_DEBUG(" DIMM: %d\n", i);
- if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
+ if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- }
current_cas_mask = spd_read_byte(device, SPD_ACCEPTABLE_CAS_LATENCIES);
while (current_cas_mask) {
int highest_supported_cas = 0, current_cas = 0;
PRINTK_DEBUG(" Current CAS mask: %04x; ", current_cas_mask);
- if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
+ if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5)
highest_supported_cas = 5;
- } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
+ else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4)
highest_supported_cas = 4;
- } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
+ else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3)
highest_supported_cas = 3;
- } else {
+ else
die("Invalid max. CAS.\n");
- }
- if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
+ if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3)
current_cas = 3;
- } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
+ else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4)
current_cas = 4;
- } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
+ else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5)
current_cas = 5;
- } else {
+ else
die("Invalid CAS.\n");
- }
idx = highest_supported_cas - current_cas;
PRINTK_DEBUG("idx=%d, ", idx);
@@ -572,17 +574,19 @@
PRINTK_DEBUG(" freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask);
if (freq_cas_mask) {
switch (j) {
- case 0: sysinfo->memory_frequency = 400; break;
- case 1: sysinfo->memory_frequency = 533; break;
- case 2: sysinfo->memory_frequency = 667; break;
+ case 0:
+ sysinfo->memory_frequency = 400; break;
+ case 1:
+ sysinfo->memory_frequency = 533; break;
+ case 2:
+ sysinfo->memory_frequency = 667; break;
}
- if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
+ if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3)
sysinfo->cas = 3;
- } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
+ else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4)
sysinfo->cas = 4;
- } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
+ else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5)
sysinfo->cas = 5;
- }
break;
}
}
@@ -595,7 +599,7 @@
}
}
-static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
+static void sdram_detect_smallest_tRAS(struct sys_info *sysinfo)
{
int i;
int tRAS_time;
@@ -603,9 +607,12 @@
int freq_multiplier = 0;
switch (sysinfo->memory_frequency) {
- case 400: freq_multiplier = 0x14; break; /* 5ns */
- case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
- case 667: freq_multiplier = 0x0c; break; /* 3ns */
+ case 400:
+ freq_multiplier = 0x14; break; /* 5ns */
+ case 533:
+ freq_multiplier = 0x0f; break; /* 3.75ns */
+ case 667:
+ freq_multiplier = 0x0c; break; /* 3ns */
}
tRAS_cycles = 4; /* 4 clocks minimum */
@@ -618,24 +625,22 @@
continue;
reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
- if (!reg8) {
+ if (!reg8)
die("Invalid tRAS value.\n");
- }
while ((tRAS_time >> 2) < reg8) {
tRAS_time += freq_multiplier;
tRAS_cycles++;
}
}
- if (tRAS_cycles > 0x18) {
+ if (tRAS_cycles > 0x18)
die("DDR-II Module does not support this frequency (tRAS error)\n");
- }
printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
sysinfo->tras = tRAS_cycles;
}
-static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
+static void sdram_detect_smallest_tRP(struct sys_info *sysinfo)
{
int i;
int tRP_time;
@@ -643,9 +648,12 @@
int freq_multiplier = 0;
switch (sysinfo->memory_frequency) {
- case 400: freq_multiplier = 0x14; break; /* 5ns */
- case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
- case 667: freq_multiplier = 0x0c; break; /* 3ns */
+ case 400:
+ freq_multiplier = 0x14; break; /* 5ns */
+ case 533:
+ freq_multiplier = 0x0f; break; /* 3.75ns */
+ case 667:
+ freq_multiplier = 0x0c; break; /* 3ns */
}
tRP_cycles = 2; /* 2 clocks minimum */
@@ -658,9 +666,8 @@
continue;
reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ROW_PRECHARGE_TIME);
- if (!reg8) {
+ if (!reg8)
die("Invalid tRP value.\n");
- }
while (tRP_time < reg8) {
tRP_time += freq_multiplier;
@@ -668,15 +675,14 @@
}
}
- if (tRP_cycles > 6) {
+ if (tRP_cycles > 6)
die("DDR-II Module does not support this frequency (tRP error)\n");
- }
printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
sysinfo->trp = tRP_cycles;
}
-static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
+static void sdram_detect_smallest_tRCD(struct sys_info *sysinfo)
{
int i;
int tRCD_time;
@@ -684,9 +690,12 @@
int freq_multiplier = 0;
switch (sysinfo->memory_frequency) {
- case 400: freq_multiplier = 0x14; break; /* 5ns */
- case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
- case 667: freq_multiplier = 0x0c; break; /* 3ns */
+ case 400:
+ freq_multiplier = 0x14; break; /* 5ns */
+ case 533:
+ freq_multiplier = 0x0f; break; /* 3.75ns */
+ case 667:
+ freq_multiplier = 0x0c; break; /* 3ns */
}
tRCD_cycles = 2; /* 2 clocks minimum */
@@ -699,24 +708,22 @@
continue;
reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_RAS_TO_CAS_DELAY);
- if (!reg8) {
+ if (!reg8)
die("Invalid tRCD value.\n");
- }
while (tRCD_time < reg8) {
tRCD_time += freq_multiplier;
tRCD_cycles++;
}
}
- if (tRCD_cycles > 6) {
+ if (tRCD_cycles > 6)
die("DDR-II Module does not support this frequency (tRCD error)\n");
- }
printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
sysinfo->trcd = tRCD_cycles;
}
-static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
+static void sdram_detect_smallest_tWR(struct sys_info *sysinfo)
{
int i;
int tWR_time;
@@ -724,9 +731,12 @@
int freq_multiplier = 0;
switch (sysinfo->memory_frequency) {
- case 400: freq_multiplier = 0x14; break; /* 5ns */
- case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
- case 667: freq_multiplier = 0x0c; break; /* 3ns */
+ case 400:
+ freq_multiplier = 0x14; break; /* 5ns */
+ case 533:
+ freq_multiplier = 0x0f; break; /* 3.75ns */
+ case 667:
+ freq_multiplier = 0x0c; break; /* 3ns */
}
tWR_cycles = 2; /* 2 clocks minimum */
@@ -739,24 +749,22 @@
continue;
reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_WRITE_RECOVERY_TIME);
- if (!reg8) {
+ if (!reg8)
die("Invalid tWR value.\n");
- }
while (tWR_time < reg8) {
tWR_time += freq_multiplier;
tWR_cycles++;
}
}
- if (tWR_cycles > 5) {
+ if (tWR_cycles > 5)
die("DDR-II Module does not support this frequency (tWR error)\n");
- }
printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
sysinfo->twr = tWR_cycles;
}
-static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
+static void sdram_detect_smallest_tRFC(struct sys_info *sysinfo)
{
int i, index = 0;
@@ -764,7 +772,7 @@
/* 75 105 127.5 */
15, 21, 26, /* DDR2-400 */
20, 28, 34, /* DDR2-533 */
- 25, 35, 43 /* DDR2-667 */
+ 25, 35, 43 /* DDR2-667 */
};
for (i = 0; i < 2*DIMM_SOCKETS; i++) {
@@ -775,10 +783,14 @@
reg8 = sysinfo->banksize[i*2];
switch (reg8) {
- case 0x04: reg8 = 0; break;
- case 0x08: reg8 = 1; break;
- case 0x10: reg8 = 2; break;
- case 0x20: reg8 = 3; break;
+ case 0x04:
+ reg8 = 0; break;
+ case 0x08:
+ reg8 = 1; break;
+ case 0x10:
+ reg8 = 2; break;
+ case 0x20:
+ reg8 = 3; break;
}
if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
@@ -798,16 +810,19 @@
}
index--;
switch (sysinfo->memory_frequency) {
- case 667: index += 3; /* Fallthrough */
- case 533: index += 3; /* Fallthrough */
- case 400: break;
+ case 667:
+ index += 3; /* Fallthrough */
+ case 533:
+ index += 3; /* Fallthrough */
+ case 400:
+ break;
}
sysinfo->trfc = tRFC_cycles[index];
printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
}
-static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
+static void sdram_detect_smallest_refresh(struct sys_info *sysinfo)
{
int i;
@@ -840,7 +855,7 @@
printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
}
-static void sdram_verify_burst_length(struct sys_info * sysinfo)
+static void sdram_verify_burst_length(struct sys_info *sysinfo)
{
int i;
@@ -854,7 +869,7 @@
}
}
-static void sdram_program_dram_width(struct sys_info * sysinfo)
+static void sdram_program_dram_width(struct sys_info *sysinfo)
{
u16 c0dramw = 0, c1dramw = 0;
int idx;
@@ -865,22 +880,32 @@
idx = 1;
switch (sysinfo->dimm[0]) {
- case 0: c0dramw = 0x0000; break; /* x16DS */
- case 1: c0dramw = 0x0001; break; /* x8DS */
- case 2: c0dramw = 0x0000; break; /* x16SS */
- case 3: c0dramw = 0x0005; break; /* x8DDS */
- case 4: c0dramw = 0x0000; break; /* NC */
+ case 0:
+ c0dramw = 0x0000; break; /* x16DS */
+ case 1:
+ c0dramw = 0x0001; break; /* x8DS */
+ case 2:
+ c0dramw = 0x0000; break; /* x16SS */
+ case 3:
+ c0dramw = 0x0005; break; /* x8DDS */
+ case 4:
+ c0dramw = 0x0000; break; /* NC */
}
switch (sysinfo->dimm[idx]) {
- case 0: c1dramw = 0x0000; break; /* x16DS */
- case 1: c1dramw = 0x0010; break; /* x8DS */
- case 2: c1dramw = 0x0000; break; /* x16SS */
- case 3: c1dramw = 0x0050; break; /* x8DDS */
- case 4: c1dramw = 0x0000; break; /* NC */
+ case 0:
+ c1dramw = 0x0000; break; /* x16DS */
+ case 1:
+ c1dramw = 0x0010; break; /* x8DS */
+ case 2:
+ c1dramw = 0x0000; break; /* x16SS */
+ case 3:
+ c1dramw = 0x0050; break; /* x8DDS */
+ case 4:
+ c1dramw = 0x0000; break; /* NC */
}
- if ( !sdram_capabilities_dual_channel() ) {
+ if (!sdram_capabilities_dual_channel()) {
/* Single Channel */
c0dramw |= c1dramw;
c1dramw = 0;
@@ -1163,7 +1188,7 @@
static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
{
- const u8 * strength_multiplier;
+ const u8 *strength_multiplier;
int idx, dual_channel;
/* Set Strength Multipliers */
@@ -1195,12 +1220,12 @@
/* Channel 0 */
sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0));
sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1));
- if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) {
+ if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED))
sdram_write_slew_rates(G3SRPUT, ctl3220);
- } else {
+ else
sdram_write_slew_rates(G3SRPUT, slew_group_lookup(dual_channel, idx * 8 + 2));
- }
+
sdram_write_slew_rates(G4SRPUT, slew_group_lookup(dual_channel, idx * 8 + 3));
sdram_write_slew_rates(G5SRPUT, slew_group_lookup(dual_channel, idx * 8 + 4));
sdram_write_slew_rates(G6SRPUT, slew_group_lookup(dual_channel, idx * 8 + 5));
@@ -1232,21 +1257,27 @@
printk(BIOS_DEBUG, "Programming DLL Timings...\n");
- MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
+ MCHBAR16(DQSMT) &= ~((3 << 12) | (1 << 10) | (0xf << 0));
MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
/* We drive both channels with the same speed */
if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
switch (sysinfo->memory_frequency) {
- case 400: channeldll = 0x26262626; break;
- case 533: channeldll = 0x22222222; break;
- case 667: channeldll = 0x11111111; break;
+ case 400:
+ channeldll = 0x26262626; break;
+ case 533:
+ channeldll = 0x22222222; break;
+ case 667:
+ channeldll = 0x11111111; break;
}
} else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
switch (sysinfo->memory_frequency) {
- case 400: channeldll = 0x33333333; break;
- case 533: channeldll = 0x24242424; break;
- case 667: channeldll = 0x25252525; break;
+ case 400:
+ channeldll = 0x33333333; break;
+ case 533:
+ channeldll = 0x24242424; break;
+ case 667:
+ channeldll = 0x25252525; break;
}
}
@@ -1298,15 +1329,15 @@
/* Enable Data Half Clock Pushout */
reg8 = MCHBAR8(C0HCTC);
reg8 &= ~0x1f;
- reg8 |= ( 1 << 0);
+ reg8 |= (1 << 0);
MCHBAR8(C0HCTC) = reg8;
reg8 = MCHBAR8(C1HCTC);
reg8 &= ~0x1f;
- reg8 |= ( 1 << 0);
+ reg8 |= (1 << 0);
MCHBAR8(C1HCTC) = reg8;
- MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) );
+ MCHBAR16(WDLLBYPMODE) &= ~((1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1));
MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0);
MCHBAR8(C0WDLLCMC) = 0;
@@ -1319,7 +1350,7 @@
/* Indicate that RCOMP programming is done */
reg32 = MCHBAR32(GBRCOMPCTL);
- reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) );
+ reg32 &= ~((1 << 29) | (1 << 26) | (3 << 21) | (3 << 2));
reg32 |= (3 << 27) | (3 << 0);
MCHBAR32(GBRCOMPCTL) = reg32;
@@ -1404,45 +1435,58 @@
sz.side2 = 0;
rows = spd_read_byte(device, SPD_NUM_ROWS); /* rows */
- if (rows < 0) goto hw_err;
- if ((rows & 0xf) == 0) goto val_err;
+ if (rows < 0)
+ goto hw_err;
+ if ((rows & 0xf) == 0)
+ goto val_err;
sz.side1 += rows & 0xf;
columns = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */
- if (columns < 0) goto hw_err;
- if ((columns & 0xf) == 0) goto val_err;
+ if (columns < 0)
+ goto hw_err;
+ if ((columns & 0xf) == 0)
+ goto val_err;
sz.side1 += columns & 0xf;
value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */
- if (value < 0) goto hw_err;
- if ((value & 0xff) == 0) goto val_err;
+ if (value < 0)
+ goto hw_err;
+ if ((value & 0xff) == 0)
+ goto val_err;
sz.side1 += log2(value & 0xff);
/* Get the module data width and convert it to a power of two */
value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB); /* (high byte) */
- if (value < 0) goto hw_err;
+ if (value < 0)
+ goto hw_err;
value &= 0xff;
value <<= 8;
low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */
- if (low < 0) goto hw_err;
+ if (low < 0)
+ goto hw_err;
value = value | (low & 0xff);
- if ((value != 72) && (value != 64)) goto val_err;
+ if ((value != 72) && (value != 64))
+ goto val_err;
sz.side1 += log2(value);
/* side 2 */
value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); /* number of physical banks */
- if (value < 0) goto hw_err;
+ if (value < 0)
+ goto hw_err;
value &= 7;
value++;
- if (value == 1) goto out;
- if (value != 2) goto val_err;
+ if (value == 1)
+ goto out;
+ if (value != 2)
+ goto val_err;
/* Start with the symmetrical case */
sz.side2 = sz.side1;
- if ((rows & 0xf0) == 0) goto out; /* If symmetrical we are done */
+ if ((rows & 0xf0) == 0)
+ goto out; /* If symmetrical we are done */
/* Don't die here, I have not come across any of these to test what
* actually happens.
@@ -1469,7 +1513,7 @@
return sz;
}
-static void sdram_detect_dimm_size(struct sys_info * sysinfo)
+static void sdram_detect_dimm_size(struct sys_info *sysinfo)
{
int i;
@@ -1492,7 +1536,7 @@
sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
- printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
+ printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32);
if (!sz.side2)
continue;
@@ -1563,13 +1607,13 @@
tolud = MIN(((4096 - pci_mmio_size) / 128) << 3, tolud);
- pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
+ pci_write_config8(PCI_DEV(0, 0, 0), TOLUD, tolud);
printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
- printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
+ printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0, 0, 0), TOLUD));
- pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
+ pci_write_config16(PCI_DEV(0, 0, 0), TOM, tom);
return 0;
}
@@ -1584,9 +1628,8 @@
u16 device;
u8 columnsrows;
- if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
+ if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- }
device = get_dimm_spd_address(sysinfo, i);
@@ -1597,18 +1640,23 @@
columnsrows |= (value & 0xf) << 4;
switch (columnsrows) {
- case 0x9d: dra = 2; break;
- case 0xad: dra = 3; break;
- case 0xbd: dra = 4; break;
- case 0xae: dra = 3; break;
- case 0xbe: dra = 4; break;
- default: die("Unsupported Rows/Columns. (DRA)");
+ case 0x9d:
+ dra = 2; break;
+ case 0xad:
+ dra = 3; break;
+ case 0xbd:
+ dra = 4; break;
+ case 0xae:
+ dra = 3; break;
+ case 0xbe:
+ dra = 4; break;
+ default:
+ die("Unsupported Rows/Columns. (DRA)");
}
/* Double Sided DIMMs? */
- if (sysinfo->banksize[(2 * i) + 1] != 0) {
+ if (sysinfo->banksize[(2 * i) + 1] != 0)
dra = (dra << 4) | dra;
- }
if (i < DIMM_SOCKETS)
dra0 |= (dra << (i*8));
@@ -1660,11 +1708,10 @@
{
u32 reg32;
- if (sysinfo->refresh == REFRESH_7_8US) {
+ if (sysinfo->refresh == REFRESH_7_8US)
reg32 = (2 << 8); /* Refresh enabled at 7.8us */
- } else {
+ else
reg32 = (1 << 8); /* Refresh enabled at 15.6us */
- }
MCHBAR32(C0DRC0) &= ~(7 << 8);
MCHBAR32(C0DRC0) |= reg32;
@@ -1681,9 +1728,8 @@
reg32 = MCHBAR32(C0DRC1);
for (i = 0; i < 4; i++) {
- if (sysinfo->banksize[i] == 0) {
+ if (sysinfo->banksize[i] == 0)
reg32 |= (1 << (16 + i));
- }
}
reg32 |= (1 << 12);
@@ -1695,9 +1741,8 @@
reg32 = MCHBAR32(C1DRC1);
for (i = 4; i < 8; i++) {
- if (sysinfo->banksize[i] == 0) {
+ if (sysinfo->banksize[i] == 0)
reg32 |= (1 << (12 + i));
- }
}
reg32 |= (1 << 12);
@@ -1714,18 +1759,16 @@
reg32 = MCHBAR32(C0DRC2);
for (i = 0; i < 4; i++) {
- if (sysinfo->banksize[i] == 0) {
+ if (sysinfo->banksize[i] == 0)
reg32 |= (1 << (24 + i));
- }
}
MCHBAR32(C0DRC2) = reg32;
reg32 = MCHBAR32(C1DRC2);
for (i = 4; i < 8; i++) {
- if (sysinfo->banksize[i] == 0) {
+ if (sysinfo->banksize[i] == 0)
reg32 |= (1 << (20 + i));
- }
}
MCHBAR32(C1DRC2) = reg32;
}
@@ -1753,12 +1796,12 @@
reg32 = MCHBAR32(C0DRC0);
reg32 |= (1 << 2); /* Burst Length 8 */
- reg32 &= ~( (1 << 13) | (1 << 12) );
+ reg32 &= ~((1 << 13) | (1 << 12));
MCHBAR32(C0DRC0) = reg32;
reg32 = MCHBAR32(C1DRC0);
reg32 |= (1 << 2); /* Burst Length 8 */
- reg32 &= ~( (1 << 13) | (1 << 12) );
+ reg32 &= ~((1 << 13) | (1 << 12));
MCHBAR32(C1DRC0) = reg32;
if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
@@ -1786,18 +1829,17 @@
reg32 += sysinfo->trp;
temp_drt |= (reg32 << 4);
- if (sysinfo->memory_frequency == 667) {
+ if (sysinfo->memory_frequency == 667)
tWTR = 3; /* 667MHz */
- } else {
+ else
tWTR = 2; /* 400 and 533 */
- }
/* B2B Write to Read Command Spacing */
reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
temp_drt |= (reg32 << 24);
/* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
- temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
+ temp_drt |= ((1 << 22) | (3 << 20) | (1 << 18) | (0 << 16));
/* Program Write Auto Precharge to Activate */
off32 = 0;
@@ -1861,27 +1903,24 @@
temp_drt |= (sysinfo->tras << 19);
/* Read to Precharge (tRTP) */
- if (sysinfo->memory_frequency == 667) {
+ if (sysinfo->memory_frequency == 667)
temp_drt |= (1 << 28);
- } else {
+ else
temp_drt |= (0 << 28);
- }
/* Determine page size */
reg32 = 0;
page_size = 1; /* Default: 1k pagesize */
- for (i = 0; i< 2*DIMM_SOCKETS; i++) {
+ for (i = 0; i < 2*DIMM_SOCKETS; i++) {
if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
page_size = 2; /* 2k pagesize */
}
- if (sysinfo->memory_frequency == 533 && page_size == 2) {
+ if (sysinfo->memory_frequency == 533 && page_size == 2)
reg32 = 1;
- }
- if (sysinfo->memory_frequency == 667) {
+ if (sysinfo->memory_frequency == 667)
reg32 = page_size;
- }
temp_drt |= (reg32 << 30);
@@ -1933,10 +1972,10 @@
printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
if (sdram_capabilities_interleave() &&
- ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
- sysinfo->banksize[2] + sysinfo->banksize[3] ) ==
- ( sysinfo->banksize[4] + sysinfo->banksize[5] +
- sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) {
+ ((sysinfo->banksize[0] + sysinfo->banksize[1] +
+ sysinfo->banksize[2] + sysinfo->banksize[3]) ==
+ (sysinfo->banksize[4] + sysinfo->banksize[5] +
+ sysinfo->banksize[6] + sysinfo->banksize[7]))) {
/* Both channels equipped with DIMMs of the same size */
sysinfo->interleaved = 1;
} else {
@@ -1985,9 +2024,12 @@
/* Program CPCTL according to FSB speed */
/* Only write the lower byte */
switch (sysinfo->fsb_frequency) {
- case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
- case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
- case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
+ case 400:
+ MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
+ case 533:
+ MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
+ case 667:
+ MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
}
MCHBAR16(CPCTL) &= ~(1 << 11);
@@ -2022,9 +2064,9 @@
printk(BIOS_DEBUG, "Voltage: %s ", (voltage == VOLTAGE_1_05)?"1.05V":"1.5V");
/* Gate graphics hardware for frequency change */
- reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
+ reg8 = pci_read_config16(PCI_DEV(0, 2, 0), GCFC + 1);
reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */
- pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
+ pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);
/* Get graphics frequency capabilities */
reg8 = sdram_capabilities_core_frequencies();
@@ -2037,31 +2079,37 @@
else
freq = CRCLK_400MHz; /* 1.5V requires 400MHz */
break;
- case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
- case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
- case GFX_FREQUENCY_CAP_166MHZ: freq = CRCLK_166MHz; break;
+ case GFX_FREQUENCY_CAP_250MHZ:
+ freq = CRCLK_250MHz; break;
+ case GFX_FREQUENCY_CAP_200MHZ:
+ freq = CRCLK_200MHz; break;
+ case GFX_FREQUENCY_CAP_166MHZ:
+ freq = CRCLK_166MHz; break;
}
if (freq != CRCLK_400MHz) {
/* What chipset are we? Force 166MHz for GMS */
- reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
+ reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4;
if (reg8 == 2)
freq = CRCLK_166MHz;
}
printk(BIOS_DEBUG, "Render: ");
switch (freq) {
- case CRCLK_166MHz: printk(BIOS_DEBUG, "166MHz"); break;
- case CRCLK_200MHz: printk(BIOS_DEBUG, "200MHz"); break;
- case CRCLK_250MHz: printk(BIOS_DEBUG, "250MHz"); break;
- case CRCLK_400MHz: printk(BIOS_DEBUG, "400MHz"); break;
+ case CRCLK_166MHz:
+ printk(BIOS_DEBUG, "166MHz"); break;
+ case CRCLK_200MHz:
+ printk(BIOS_DEBUG, "200MHz"); break;
+ case CRCLK_250MHz:
+ printk(BIOS_DEBUG, "250MHz"); break;
+ case CRCLK_400MHz:
+ printk(BIOS_DEBUG, "400MHz"); break;
}
- if (i945_silicon_revision() == 0) {
+ if (i945_silicon_revision() == 0)
sysinfo->mvco4x = 1;
- } else {
+ else
sysinfo->mvco4x = 0;
- }
second_vco = 0;
@@ -2071,9 +2119,9 @@
u16 mem = sysinfo->memory_frequency;
u16 fsb = sysinfo->fsb_frequency;
- if ( (fsb == 667 && mem == 533) ||
- (fsb == 533 && mem == 533) ||
- (fsb == 533 && mem == 400)) {
+ if ((fsb == 667 && mem == 533) ||
+ (fsb == 533 && mem == 533) ||
+ (fsb == 533 && mem == 400)) {
second_vco = 1;
}
@@ -2081,21 +2129,20 @@
sysinfo->mvco4x = 1;
}
- if (second_vco) {
+ if (second_vco)
sysinfo->clkcfg_bit7 = 1;
- } else {
+ else
sysinfo->clkcfg_bit7 = 0;
- }
/* Graphics Core Render Clock */
- reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
- reg16 &= ~( (7 << 0) | (1 << 13) );
+ reg16 = pci_read_config16(PCI_DEV(0, 2, 0), GCFC);
+ reg16 &= ~((7 << 0) | (1 << 13));
reg16 |= freq;
- pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
+ pci_write_config16(PCI_DEV(0, 2, 0), GCFC, reg16);
/* Graphics Core Display Clock */
- reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC);
- reg8 &= ~( (1<<7) | (7<<4) );
+ reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC);
+ reg8 &= ~((1<<7) | (7<<4));
if (voltage == VOLTAGE_1_05) {
reg8 |= CDCLK_200MHz;
@@ -2104,19 +2151,19 @@
reg8 |= CDCLK_320MHz;
printk(BIOS_DEBUG, " Display: 320MHz\n");
}
- pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
+ pci_write_config8(PCI_DEV(0, 2, 0), GCFC, reg8);
- reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
+ reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC + 1);
reg8 |= (1<<3) | (1<<1);
- pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
+ pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);
reg8 |= 0x0f;
- pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
+ pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);
/* Ungate core render and display clocks */
reg8 &= 0xf0;
- pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
+ pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);
}
static void sdram_program_memory_frequency(struct sys_info *sysinfo)
@@ -2131,7 +2178,7 @@
printk(BIOS_DEBUG, "CLKCFG = 0x%08x, ", clkcfg);
- clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
+ clkcfg &= ~((1 << 12) | (1 << 7) | (7 << 4));
if (sysinfo->mvco4x) {
printk(BIOS_DEBUG, "MVCO 4x, ");
@@ -2145,10 +2192,14 @@
}
switch (sysinfo->memory_frequency) {
- case 400: clkcfg |= ((1 + offset) << 4); break;
- case 533: clkcfg |= ((2 + offset) << 4); break;
- case 667: clkcfg |= ((3 + offset) << 4); break;
- default: die("Target Memory Frequency Error");
+ case 400:
+ clkcfg |= ((1 + offset) << 4); break;
+ case 533:
+ clkcfg |= ((2 + offset) << 4); break;
+ case 667:
+ clkcfg |= ((3 + offset) << 4); break;
+ default:
+ die("Target Memory Frequency Error");
}
if (MCHBAR32(CLKCFG) == clkcfg) {
@@ -2163,7 +2214,7 @@
*/
goto cache_code;
vco_update:
- reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
reg8 &= ~(1 << 7);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
@@ -2300,25 +2351,34 @@
printk(BIOS_DEBUG, "MEM=");
switch (memclk()) {
- case 400: printk(BIOS_DEBUG, "400"); idx += 0; break;
- case 533: printk(BIOS_DEBUG, "533"); idx += 2; break;
- case 667: printk(BIOS_DEBUG, "667"); idx += 4; break;
- default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
+ case 400:
+ printk(BIOS_DEBUG, "400"); idx += 0; break;
+ case 533:
+ printk(BIOS_DEBUG, "533"); idx += 2; break;
+ case 667:
+ printk(BIOS_DEBUG, "667"); idx += 4; break;
+ default:
+ printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
}
printk(BIOS_DEBUG, " FSB=");
switch (fsbclk()) {
- case 400: printk(BIOS_DEBUG, "400"); idx += 0; break;
- case 533: printk(BIOS_DEBUG, "533"); idx += 6; break;
- case 667: printk(BIOS_DEBUG, "667"); idx += 12; break;
- case 800: printk(BIOS_DEBUG, "800"); idx += 18; break;
- case 1066: printk(BIOS_DEBUG, "1066"); idx += 24; break;
- default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
+ case 400:
+ printk(BIOS_DEBUG, "400"); idx += 0; break;
+ case 533:
+ printk(BIOS_DEBUG, "533"); idx += 6; break;
+ case 667:
+ printk(BIOS_DEBUG, "667"); idx += 12; break;
+ case 800:
+ printk(BIOS_DEBUG, "800"); idx += 18; break;
+ case 1066:
+ printk(BIOS_DEBUG, "1066"); idx += 24; break;
+ default:
+ printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
}
- if (command_clock_crossing[idx]==0xffffffff) {
+ if (command_clock_crossing[idx] == 0xffffffff)
printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
- }
MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
@@ -2394,63 +2454,55 @@
if (!sysinfo->interleaved) {
/* Single Channel & Dual Channel Asymmetric */
if (chan0_populated) {
- if (chan0_dualsided) {
+ if (chan0_dualsided)
chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
- } else {
+ else
chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE;
- }
}
if (chan1_populated) {
- if (chan1_dualsided) {
+ if (chan1_dualsided)
chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
- } else {
+ else
chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE;
- }
}
} else {
/* Interleaved has always both channels populated */
- if (chan0_dualsided) {
+ if (chan0_dualsided)
chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
- } else {
+ else
chan0 = EA_DUALCHANNEL_XOR_BANK_MODE;
- }
- if (chan1_dualsided) {
+ if (chan1_dualsided)
chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
- } else {
+ else
chan1 = EA_DUALCHANNEL_XOR_BANK_MODE;
- }
}
} else {
if (!sysinfo->interleaved) {
/* Single Channel & Dual Channel Asymmetric */
if (chan0_populated) {
- if (chan0_dualsided) {
+ if (chan0_dualsided)
chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;
- } else {
+ else
chan0 = EA_SINGLECHANNEL_BANK_MODE;
- }
}
if (chan1_populated) {
- if (chan1_dualsided) {
+ if (chan1_dualsided)
chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE;
- } else {
+ else
chan1 = EA_SINGLECHANNEL_BANK_MODE;
- }
}
} else {
/* Interleaved has always both channels populated */
- if (chan0_dualsided) {
+ if (chan0_dualsided)
chan0 = EA_DUALCHANNEL_BANK_RANK_MODE;
- } else {
+ else
chan0 = EA_DUALCHANNEL_BANK_MODE;
- }
- if (chan1_dualsided) {
+ if (chan1_dualsided)
chan1 = EA_DUALCHANNEL_BANK_RANK_MODE;
- } else {
+ else
chan1 = EA_DUALCHANNEL_BANK_MODE;
- }
}
}
@@ -2524,7 +2576,7 @@
reg32 |= (1 << 12) | (1 << 11);
MCHBAR32(C1DRC1) = reg32;
- if (i945_silicon_revision()>1) {
+ if (i945_silicon_revision() > 1) {
/* FIXME bits 5 and 0 only if PCIe graphics is disabled */
u16 peg_bits = (1 << 5) | (1 << 0);
@@ -2553,11 +2605,10 @@
reg16 = MCHBAR16(CPCTL);
reg16 &= ~(7 << 11);
- if (i945_silicon_revision()>2) {
+ if (i945_silicon_revision() > 2)
reg16 |= (6 << 11);
- } else {
+ else
reg16 |= (4 << 11);
- }
MCHBAR16(CPCTL) = reg16;
#if 0
@@ -2566,13 +2617,17 @@
if (i945_silicon_revision() != 0) {
#endif
switch (sysinfo->fsb_frequency) {
- case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
- case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
+ case 667:
+ MCHBAR32(HGIPMC2) = 0x0d590d59; break;
+ case 533:
+ MCHBAR32(HGIPMC2) = 0x155b155b; break;
}
} else {
switch (sysinfo->fsb_frequency) {
- case 667: MCHBAR32(HGIPMC2) = 0x09c409c4; break;
- case 533: MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
+ case 667:
+ MCHBAR32(HGIPMC2) = 0x09c409c4; break;
+ case 533:
+ MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
}
}
@@ -2581,32 +2636,34 @@
reg32 = MCHBAR32(C2C3TT);
reg32 &= 0xffff0000;
switch (sysinfo->fsb_frequency) {
- case 667: reg32 |= 0x0600; break;
- case 533: reg32 |= 0x0480; break;
+ case 667:
+ reg32 |= 0x0600; break;
+ case 533:
+ reg32 |= 0x0480; break;
}
MCHBAR32(C2C3TT) = reg32;
reg32 = MCHBAR32(C3C4TT);
reg32 &= 0xffff0000;
switch (sysinfo->fsb_frequency) {
- case 667: reg32 |= 0x0b80; break;
- case 533: reg32 |= 0x0980; break;
+ case 667:
+ reg32 |= 0x0b80; break;
+ case 533:
+ reg32 |= 0x0980; break;
}
MCHBAR32(C3C4TT) = reg32;
- if (i945_silicon_revision() == 0) {
+ if (i945_silicon_revision() == 0)
MCHBAR32(ECO) &= ~(1 << 16);
- } else {
+ else
MCHBAR32(ECO) |= (1 << 16);
- }
#if 0
- if (i945_silicon_revision() == 0) {
+ if (i945_silicon_revision() == 0)
MCHBAR32(FSBPMC3) &= ~(1 << 29);
- } else {
+ else
MCHBAR32(FSBPMC3) |= (1 << 29);
- }
#endif
MCHBAR32(FSBPMC3) &= ~(1 << 29);
@@ -2618,25 +2675,25 @@
reg32 = MCHBAR32(FSBPMC4);
reg32 &= ~(3 << 24);
- reg32 |= ( 2 << 24);
+ reg32 |= (2 << 24);
MCHBAR32(FSBPMC4) = reg32;
MCHBAR32(FSBPMC4) |= (1 << 21);
MCHBAR32(FSBPMC4) |= (1 << 5);
- if ((i945_silicon_revision() < 2) /* || cpuid() = 0x6e8 */ ) {
+ if ((i945_silicon_revision() < 2)) { /* || cpuid() = 0x6e8 */
/* stepping 0 and 1 or CPUID 6e8 */
MCHBAR32(FSBPMC4) &= ~(1 << 4);
} else {
MCHBAR32(FSBPMC4) |= (1 << 4);
}
- reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
+ reg8 = pci_read_config8(PCI_DEV(0, 0x0, 0), 0xfc);
reg8 |= (1 << 4);
pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
- reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
+ reg8 = pci_read_config8(PCI_DEV(0, 0x2, 0), 0xc1);
reg8 |= (1 << 2);
pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
@@ -2703,8 +2760,8 @@
* area and restored instead of recalculated in case
* of an S3 resume.
*
- * C0WL0REOST [7:0] -> 8 bit
- * C1WL0REOST [7:0] -> 8 bit
+ * C0WL0REOST [7:0] -> 8 bit
+ * C1WL0REOST [7:0] -> 8 bit
* RCVENMT [11:8] [3:0] -> 8 bit
* C0DRT1 [27:24] -> 4 bit
* C1DRT1 [27:24] -> 4 bit
@@ -2799,8 +2856,8 @@
reg32 |= (1 << 14) | (1 << 6) | (2 << 16);
MCHBAR32(ODTC) = reg32;
- if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
- sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
+ if (!(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
+ sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) {
printk(BIOS_DEBUG, "one dimm per channel config..\n");
reg32 = MCHBAR32(C0ODT);
@@ -2871,11 +2928,11 @@
}
#define RTT_ODT_NONE 0
-#define RTT_ODT_50_OHM ( (1 << 9) | (1 << 5) )
+#define RTT_ODT_50_OHM ((1 << 9) | (1 << 5))
#define RTT_ODT_75_OHM (1 << 5)
#define RTT_ODT_150_OHM (1 << 9)
-#define EMRS_OCD_DEFAULT ( (1 << 12) | (1 << 11) | (1 << 10) )
+#define EMRS_OCD_DEFAULT ((1 << 12) | (1 << 11) | (1 << 10))
#define MRS_CAS_3 (3 << 7)
#define MRS_CAS_4 (4 << 7)
@@ -2896,9 +2953,8 @@
u32 bankaddr = 0, tmpaddr, mrsaddr = 0;
for (i = 0, nonzero = -1; i < 8; i++) {
- if (sysinfo->banksize[i] == 0) {
+ if (sysinfo->banksize[i] == 0)
continue;
- }
printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
switch (i) {
@@ -2929,27 +2985,34 @@
/* Get CAS latency set up */
switch (sysinfo->cas) {
- case 5: mrsaddr = MRS_CAS_5; break;
- case 4: mrsaddr = MRS_CAS_4; break;
- case 3: mrsaddr = MRS_CAS_3; break;
- default: die("Jedec Error (CAS).\n");
+ case 5:
+ mrsaddr = MRS_CAS_5; break;
+ case 4:
+ mrsaddr = MRS_CAS_4; break;
+ case 3:
+ mrsaddr = MRS_CAS_3; break;
+ default:
+ die("Jedec Error (CAS).\n");
}
/* Get tWR set */
switch (sysinfo->twr) {
- case 5: mrsaddr |= MRS_TWR_5; break;
- case 4: mrsaddr |= MRS_TWR_4; break;
- case 3: mrsaddr |= MRS_TWR_3; break;
- default: die("Jedec Error (tWR).\n");
+ case 5:
+ mrsaddr |= MRS_TWR_5; break;
+ case 4:
+ mrsaddr |= MRS_TWR_4; break;
+ case 3:
+ mrsaddr |= MRS_TWR_3; break;
+ default:
+ die("Jedec Error (tWR).\n");
}
/* Set "Burst Type" */
mrsaddr |= MRS_BT;
/* Interleaved */
- if (sysinfo->interleaved) {
+ if (sysinfo->interleaved)
mrsaddr = mrsaddr << 1;
- }
/* Only burst length 8 supported */
mrsaddr |= MRS_BL8;
@@ -2978,13 +3041,12 @@
PRINTK_DEBUG("Extended Mode Register Set\n");
do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
tmpaddr = bankaddr;
- if (!sdram_capabilities_dual_channel()) {
+ if (!sdram_capabilities_dual_channel())
tmpaddr |= RTT_ODT_75_OHM;
- } else if (sysinfo->interleaved) {
+ else if (sysinfo->interleaved)
tmpaddr |= (RTT_ODT_150_OHM << 1);
- } else {
+ else
tmpaddr |= RTT_ODT_150_OHM;
- }
ram_read32(tmpaddr);
/* Mode Register Set: Reset DLLs */
@@ -3025,14 +3087,12 @@
do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
tmpaddr = bankaddr;
- if (!sdram_capabilities_dual_channel()) {
-
+ if (!sdram_capabilities_dual_channel())
tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT;
- } else if (sysinfo->interleaved) {
+ else if (sysinfo->interleaved)
tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1);
- } else {
+ else
tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT;
- }
ram_read32(tmpaddr);
/* Extended Mode Register Set */
@@ -3040,13 +3100,12 @@
do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
tmpaddr = bankaddr;
- if (!sdram_capabilities_dual_channel()) {
+ if (!sdram_capabilities_dual_channel())
tmpaddr |= RTT_ODT_75_OHM;
- } else if (sysinfo->interleaved) {
+ else if (sysinfo->interleaved)
tmpaddr |= (RTT_ODT_150_OHM << 1);
- } else {
+ else
tmpaddr |= RTT_ODT_150_OHM;
- }
ram_read32(tmpaddr);
}
}
@@ -3204,7 +3263,7 @@
sdram_enable_rcomp();
/* Tell ICH7 that we're done */
- reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
reg8 &= ~(1 << 7);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index a6aaefa..07580d1 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -33,11 +33,10 @@
addr = 0;
if (channel_offset != 0) { /* must be dual channel */
- if (sysinfo->interleaved == 1) {
+ if (sysinfo->interleaved == 1)
addr |= (1 << 6);
- } else {
+ else
addr = ((u32)MCHBAR8(C0DRB3)) << 25;
- }
}
for (i = 0; i < 28; i++) {
@@ -46,9 +45,8 @@
}
reg32 = MCHBAR32(RCVENMT);
- if (channel_offset == 0) {
+ if (channel_offset == 0)
reg32 = reg32 << 2;
- }
/**
* [19] = 1: all bits are high
@@ -99,7 +97,7 @@
}
-static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine)
+static int normalize(int channel_offset, u8 *mediumcoarse, u8 *fine)
{
printk(BIOS_SPEW, " normalize()\n");
@@ -122,7 +120,7 @@
return 0;
}
-static int find_preamble(int channel_offset, u8 * mediumcoarse,
+static int find_preamble(int channel_offset, u8 *mediumcoarse,
struct sys_info *sysinfo)
{
/* find start of the data phase */
@@ -156,7 +154,7 @@
* add a quarter clock to the current receive enable settings
*/
-static int add_quarter_clock(int channel_offset, u8 * mediumcoarse, u8 * fine)
+static int add_quarter_clock(int channel_offset, u8 *mediumcoarse, u8 *fine)
{
printk(BIOS_SPEW, " add_quarter_clock() mediumcoarse=%02x fine=%02x\n",
*mediumcoarse, *fine);
@@ -180,7 +178,7 @@
return 0;
}
-static int find_strobes_low(int channel_offset, u8 * mediumcoarse, u8 * fine,
+static int find_strobes_low(int channel_offset, u8 *mediumcoarse, u8 *fine,
struct sys_info *sysinfo)
{
u32 rcvenmt;
@@ -214,7 +212,7 @@
return 0;
}
-static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine,
+static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine,
struct sys_info *sysinfo)
{
@@ -313,9 +311,8 @@
/* This is a debug check to see if the rcven code is fully working.
* It can be removed when the output message is not printed anymore
*/
- if (MCHBAR8(C0WL0REOST + channel_offset) == 0) {
+ if (MCHBAR8(C0WL0REOST + channel_offset) == 0)
printk(BIOS_DEBUG, "Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
- }
return 0;
}
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index 27e616b..90f2638 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -65,9 +65,8 @@
tsc1 = rdtsc();
dword = tsc1.lo + tscd.lo;
- if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+ if ((dword < tsc1.lo) || (dword < tscd.lo))
tsc1.hi++;
- }
tsc1.lo = dword;
tsc1.hi += tscd.hi;
--
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Gerrit-MessageType: merged
Gerrit-Change-Id: Ic2dd40e73d4a4c091c5ce1f49bbf9ab4d013d7af
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)
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