[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Create API to read SPI Flash MMIO register

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/18921 )

Change subject: soc/intel/skylake: Create API to read SPI Flash MMIO register
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Patch Set 3:

(2 comments)

https://review.coreboot.org/#/c/18921/3/src/soc/intel/skylake/include/soc/spi.h
File src/soc/intel/skylake/include/soc/spi.h:

PS3, Line 81: #define SPIBAR_BFPREG		0x00
            : #define  SPIBAR_BFPREG_PRB_MASK	(0x7fff)
            : #define  SPIBAR_BFPREG_PRL_SHIFT	(16)
            : #define  SPIBAR_BFPREG_PRL_MASK	(0x7fff << SPIBAR_BFPREG_PRL_SHIFT)
            : #define  SPIBAR_BFPREG_SBRS		(1 << 31)
> i didn't get your review comment correctly but in order to get BIOS region 
I meant would it be better to put these register definitions in CL:18922 since you are using these registers in that CL.


PS3, Line 85: #define  SPIBAR_BFPREG_SBRS		(1 << 31)
> I could see some discrepancy here then. This bit is not reserved for sure b
I will check again to ensure I have the latest EDS.


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Gerrit-MessageType: comment
Gerrit-Change-Id: I43400aa7204c27c73fd70e93027005d19def56ac
Gerrit-PatchSet: 3
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