[coreboot-gerrit] Change in coreboot[master]: ramstage: Align stack to 16 bytes

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18823 )

Change subject: ramstage: Align stack to 16 bytes
......................................................................


ramstage: Align stack to 16 bytes

Some SSE instructions could take 128bit memory operands from
stack.

AGESA vendorcode was always built with SSE enabled, but until
now stack alignment was not known to cause major issues. Seems
like GCC-6.3 more likely emits instructions that depend on the
16 byte alignment of stack.

Change-Id: Iea3de54f20ff242105bce5a5edbbd76b04c0116c
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
Reviewed-on: https://review.coreboot.org/18823
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
M src/arch/x86/c_start.S
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Aaron Durbin: Looks good to me, approved
  Paul Menzel: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified



diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 29d3a53..9ad2698 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -110,6 +110,8 @@
 	 */
 	post_code(POST_PRE_HARDWAREMAIN)	/* post fe */
 
+	andl	$0xFFFFFFF0, %esp
+
 #if CONFIG_GDB_WAIT
 	call gdb_hw_init
 	call gdb_stub_breakpoint

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: Iea3de54f20ff242105bce5a5edbbd76b04c0116c
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki at gmail.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)