[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add cache as ram init and teardown code

[gerrit code review]

>From Subrata Banik <subrata.banik at intel.com>:

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18381 )

Change subject: soc/intel/common/block: Add cache as ram init and teardown code
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Patch Set 28:

(2 comments)

https://review.coreboot.org/#/c/18381/28/src/soc/intel/common/block/cpu/Kconfig
File src/soc/intel/common/block/cpu/Kconfig:

Line 10: 	depends on !FSP_CAR
> We shouldn't be dealing with this option in this code. The proper selection
got it. will modify


https://review.coreboot.org/#/c/18381/28/src/soc/intel/common/block/cpu/car/cache_as_ram.S
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

Line 443: 	movl	$MTRR_PHYS_BASE(1), %ecx	/* setup variable mtrr */
> This is overwriting the MTRR when CONFIG_DCACHE_RAM_SIZE == 768 * KiB is us
we will look closely as you mention. I believe CONFIG_DCACHE_RAM_SIZE == 768 * KiB is a dedicated case for Small core and the duplication of work that you have mentioned is inside big core NEM_ENHANCED mode. we may need to pay some more attention as well while defining the path.


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Gerrit-MessageType: comment
Gerrit-Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Gerrit-PatchSet: 28
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>
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