[coreboot-gerrit] Patch set updated for coreboot: AGESA: BIST is already preserved

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18625

-gerrit

commit bac6f8b83606bc2a11af02c8ab97a03fa5b6a30c
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Wed Nov 23 21:29:26 2016 +0200

    AGESA: BIST is already preserved
    
    Officialy we enter with BIST in %eax, but %ebp is old backup register.
    Note that post_code() destroys %al.
    
    Change-Id: I77b9a80aac11ae301fdda71c2a20803d7a5fb888
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/amd/agesa/cache_as_ram.inc | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index 2a9beb8..1258d15 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -28,7 +28,6 @@
 
 /*
  * XMM map:
- *   xmm0: BIST
  */
 
 .code32
@@ -36,6 +35,9 @@
 
 cache_as_ram_setup:
 
+  /* Preserve BIST. */
+  movl %eax, %ebp
+
   post_code(0xa0)
 
   /* enable SSE2 128bit instructions */
@@ -45,11 +47,9 @@ cache_as_ram_setup:
   orl $(3<<9), %eax
   movl %eax, %cr4
 
-  /* Save the BIST result */
-  cvtsi2sd  %ebp, %xmm0
-
   post_code(0xa1)
 
+  /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */
   AMD_ENABLE_STACK
 
   /* Align the stack. */
@@ -100,16 +100,15 @@ cache_as_ram_setup:
 
 #endif
 
-  call early_all_cores
+  /* Calling conventions preserve BIST in %ebp. */
 
-  /* Restore the BIST result */
-  cvtsd2si  %xmm0, %edx
+  call early_all_cores
 
   /* Must maintain 16-byte stack alignment here. */
   pushl $0x0
   pushl $0x0
   pushl $0x0
-  pushl %edx  /* bist */
+  pushl %ebp
   call  romstage_main
 
   /* Should never see this postcode */