[coreboot-gerrit] Patch set updated for coreboot: AGESA: Disable CAR with empty stack
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Tue Mar 7 18:05:14 CET 2017
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18626
-gerrit
commit 1312ff2592e4aa24f485dad34413e152ca3f6e26
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Nov 23 06:47:15 2016 +0200
AGESA: Disable CAR with empty stack
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.
SSE2 is no longer required.
Change-Id: I986bb7a88f53f7f7a0b05d4edcd5020f5dbeb4b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/amd/agesa/cache_as_ram.inc | 43 ++++++++++++++-------------------
src/cpu/amd/agesa/family12/romstage.c | 5 ----
src/cpu/amd/agesa/family14/romstage.c | 11 ---------
src/cpu/amd/agesa/family15/romstage.c | 11 ---------
src/cpu/amd/agesa/family15rl/romstage.c | 10 --------
src/cpu/amd/agesa/family15tn/romstage.c | 11 ---------
src/cpu/amd/agesa/family16kb/romstage.c | 11 ---------
src/cpu/amd/agesa/romstage.c | 36 +++++++++++++++++++++++++--
src/cpu/amd/agesa/s3_resume.c | 2 +-
src/cpu/amd/agesa/s3_resume.h | 1 +
src/include/cpu/amd/car.h | 1 +
11 files changed, 55 insertions(+), 87 deletions(-)
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index c641afa..f43e6a4 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -26,12 +26,8 @@
#include "gcccar.inc"
#include <cpu/x86/cache.h>
-/*
- * XMM map:
- */
-
.code32
-.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
+.globl cache_as_ram_setup, cache_as_ram_setup_out
cache_as_ram_setup:
@@ -40,13 +36,6 @@ cache_as_ram_setup:
post_code(0xa0)
- /* enable SSE2 128bit instructions */
- /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
-
- movl %cr4, %eax
- orl $(3<<9), %eax
- movl %eax, %cr4
-
post_code(0xa1)
/* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */
@@ -106,6 +95,7 @@ cache_as_ram_setup:
movl %ebp, %edi
call romstage_main
+ movl %eax, %ebx
.code32
@@ -117,19 +107,15 @@ cache_as_ram_setup:
pushl %ebp
call romstage_main
+ movl %eax, %ebx
#endif
- /* Should never see this postcode */
- post_code(0xaf)
-stop:
- jmp stop
+/* Register %ebx is new stacktop for remaining of romstage.
+ * It is the only register preserved in AMD_DISABLE_STACK.
+ */
disable_cache_as_ram:
- /* Save return stack */
- movd 0(%esp), %xmm1
- movd %esp, %xmm0
-
/* Disable cache */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
@@ -141,13 +127,20 @@ disable_cache_as_ram:
movl %cr0, %eax
andl $0x9fffffff, %eax
movl %eax, %cr0
- xorl %eax, %eax
- /* Restore the return stack */
wbinvd
- movd %xmm0, %esp
- movd %xmm1, (%esp)
- ret
+
+#ifdef __x86_64__
+.code64
+#endif
+
+ movl %ebx, %esp
+ call romstage_after_car
+
+ /* Should never see this postcode */
+ post_code(0xaf)
+stop:
+ jmp stop
cache_as_ram_setup_out:
#ifdef __x86_64__
diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c
index 427d8a7..c616ed7 100644
--- a/src/cpu/amd/agesa/family12/romstage.c
+++ b/src/cpu/amd/agesa/family12/romstage.c
@@ -13,8 +13,6 @@
* GNU General Public License for more details.
*/
-#include <arch/stages.h>
-
#include <console/console.h>
#include <cpu/amd/car.h>
@@ -58,7 +56,4 @@ void agesa_main(struct sysinfo *cb)
post_code(0x40);
agesawrapper_amdinitenv();
-
- post_code(0x43);
- copy_and_run();
}
diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c
index d73b67c..6bbd496 100644
--- a/src/cpu/amd/agesa/family14/romstage.c
+++ b/src/cpu/amd/agesa/family14/romstage.c
@@ -13,9 +13,6 @@
* GNU General Public License for more details.
*/
-#include <arch/stages.h>
-#include <cpu/amd/agesa/s3_resume.h>
-
#include <console/console.h>
#include <cpu/amd/car.h>
@@ -69,13 +66,5 @@ void agesa_main(struct sysinfo *cb)
agesawrapper_amds3laterestore();
post_code(0x62);
-
- prepare_for_resume();
}
-
- post_code(0x50);
- copy_and_run();
-
- /* Not reached */
}
-
diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c
index 0ee4251..b07550c 100644
--- a/src/cpu/amd/agesa/family15/romstage.c
+++ b/src/cpu/amd/agesa/family15/romstage.c
@@ -15,8 +15,6 @@
#include <lib.h>
#include <reset.h>
-#include <arch/stages.h>
-#include <cpu/amd/agesa/s3_resume.h>
#include <console/console.h>
#include <cpu/amd/car.h>
@@ -76,13 +74,4 @@ void agesa_main(struct sysinfo *cb)
agesawrapper_amdinitenv();
post_code(0x42);
- post_code(0x50);
- print_debug("Disabling cache as ram ");
- disable_cache_as_ram();
- print_debug("done\n");
-
- post_code(0x51);
- copy_and_run();
-
- /* Not reached */
}
diff --git a/src/cpu/amd/agesa/family15rl/romstage.c b/src/cpu/amd/agesa/family15rl/romstage.c
index addba08..a9b7bb5 100644
--- a/src/cpu/amd/agesa/family15rl/romstage.c
+++ b/src/cpu/amd/agesa/family15rl/romstage.c
@@ -13,9 +13,6 @@
* GNU General Public License for more details.
*/
-#include <arch/stages.h>
-#include <cpu/amd/agesa/s3_resume.h>
-
#include <console/console.h>
#include <cpu/amd/car.h>
@@ -47,8 +44,6 @@ void agesa_main(struct sysinfo *cb)
post_code(0x41);
agesawrapper_amdinitenv();
-
- disable_cache_as_ram();
} else {
printk(BIOS_INFO, "S3 detected\n");
@@ -59,12 +54,7 @@ void agesa_main(struct sysinfo *cb)
agesawrapper_amds3laterestore();
post_code(0x61);
- prepare_for_resume();
}
- post_code(0x50);
- copy_and_run();
-
- /* Not reached */
}
diff --git a/src/cpu/amd/agesa/family15tn/romstage.c b/src/cpu/amd/agesa/family15tn/romstage.c
index d3880d3..8766e21 100644
--- a/src/cpu/amd/agesa/family15tn/romstage.c
+++ b/src/cpu/amd/agesa/family15tn/romstage.c
@@ -14,9 +14,6 @@
* GNU General Public License for more details.
*/
-#include <arch/stages.h>
-#include <cpu/amd/agesa/s3_resume.h>
-
#include <console/console.h>
#include <cpu/amd/car.h>
@@ -49,8 +46,6 @@ void agesa_main(struct sysinfo *cb)
post_code(0x41);
agesawrapper_amdinitenv();
-
- disable_cache_as_ram();
} else {
printk(BIOS_INFO, "S3 detected\n");
@@ -61,11 +56,5 @@ void agesa_main(struct sysinfo *cb)
agesawrapper_amds3laterestore();
post_code(0x61);
- prepare_for_resume();
}
-
- post_code(0x50);
- copy_and_run();
-
- /* Not reached */
}
diff --git a/src/cpu/amd/agesa/family16kb/romstage.c b/src/cpu/amd/agesa/family16kb/romstage.c
index c22ddc1..8409556 100644
--- a/src/cpu/amd/agesa/family16kb/romstage.c
+++ b/src/cpu/amd/agesa/family16kb/romstage.c
@@ -13,9 +13,6 @@
* GNU General Public License for more details.
*/
-#include <arch/stages.h>
-#include <cpu/amd/agesa/s3_resume.h>
-
#include <console/console.h>
#include <cpu/amd/car.h>
@@ -48,8 +45,6 @@ void agesa_main(struct sysinfo *cb)
post_code(0x41);
agesawrapper_amdinitenv();
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
} else {
printk(BIOS_INFO, "S3 detected\n");
@@ -60,12 +55,6 @@ void agesa_main(struct sysinfo *cb)
agesawrapper_amds3laterestore();
post_code(0x61);
- prepare_for_resume();
}
-
- post_code(0x50);
- copy_and_run();
-
- /* Not reached */
}
diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c
index d4a6b58..922371a 100644
--- a/src/cpu/amd/agesa/romstage.c
+++ b/src/cpu/amd/agesa/romstage.c
@@ -13,11 +13,17 @@
#include <arch/acpi.h>
#include <arch/cpu.h>
+#include <cbmem.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/x86/bist.h>
+#include <cpu/x86/mtrr.h>
#include <console/console.h>
+#include <halt.h>
+#include <program_loading.h>
#include <smp/node.h>
#include <string.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
static void fill_sysinfo(struct sysinfo *cb)
@@ -50,6 +56,32 @@ void * asmlinkage romstage_main(unsigned long bist)
agesa_main(cb);
- /* Not reached */
- return NULL;
+ uintptr_t stack_top = CACHE_TMP_RAMTOP;
+ if (cb->s3resume) {
+ if (!cbmem_recovery(1)) {
+ printk(BIOS_EMERG, "Unable to recover CBMEM\n");
+ halt();
+ }
+ stack_top = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE,
+ ROMSTAGE_STACK_CBMEM);
+ stack_top += HIGH_ROMSTAGE_STACK_SIZE;
+ }
+
+ printk(BIOS_DEBUG, "Move CAR stack.\n");
+ return (void*)stack_top;
+}
+
+void asmlinkage romstage_after_car(void)
+{
+ struct sysinfo romstage_state;
+ struct sysinfo *cb = &romstage_state;
+
+ printk(BIOS_DEBUG, "CAR disabled.\n");
+
+ fill_sysinfo(cb);
+
+ if (cb->s3resume)
+ set_resume_cache();
+
+ run_ramstage();
}
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index f45ff3c..8aaa25b 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -51,7 +51,7 @@ static void move_stack_high_mem(void)
#endif
}
-static void set_resume_cache(void)
+void set_resume_cache(void)
{
msr_t msr;
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
index b10489e..bb65af3 100644
--- a/src/cpu/amd/agesa/s3_resume.h
+++ b/src/cpu/amd/agesa/s3_resume.h
@@ -18,6 +18,7 @@
void restore_mtrr(void);
void prepare_for_resume(void);
+void set_resume_cache(void);
void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size);
const void *OemS3Saved_MTRR_Storage(void);
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
index 11fb8ae..df03513 100644
--- a/src/include/cpu/amd/car.h
+++ b/src/include/cpu/amd/car.h
@@ -19,5 +19,6 @@ void disable_cache_as_ram(void);
void asmlinkage early_all_cores(void);
void * asmlinkage romstage_main(unsigned long bist);
+void asmlinkage romstage_after_car(void);
#endif
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