[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: storage: Use word access for power state ...

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/20364


Change subject: soc/intel/skylake: storage: Use word access for power state registers
......................................................................

soc/intel/skylake: storage: Use word access for power state registers

In the D0 and D3 ACPI methods use word access to the PME status and
control register.  This brings the code inline with the Intel reference
code and matches how the kernel handles access to this register.

BUG=b:35587084
BRANCH=eve
TEST=manual stress testing of D0<>D3 transition across multiple devices

Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
M src/soc/intel/skylake/acpi/scs.asl
1 file changed, 15 insertions(+), 16 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/20364/1

diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl
index c2f50cc..240d2b8 100644
--- a/src/soc/intel/skylake/acpi/scs.asl
+++ b/src/soc/intel/skylake/acpi/scs.asl
@@ -21,12 +21,13 @@
 	Name (_ADR, 0x001E0004)
 	Name (_DDN, "eMMC Controller")
 	Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))
+	Name (TEMP, 0)
 
 	OperationRegion (EMCR, PCI_Config, 0x00, 0x100)
-	Field (EMCR, DWordAcc, NoLock, Preserve)
+	Field (EMCR, WordAcc, NoLock, Preserve)
 	{
 		Offset (0x84),	/* PMECTRLSTATUS */
-		D0D3, 2,	/* POWERSTATE */
+		PMCR, 16,
 		Offset (0xa2),	/* PG_CONFIG */
 		, 2,
 		PGEN, 1,	/* PG_ENABLE */
@@ -98,10 +99,9 @@
 		/* Enable Power Gate */
 		Store (1, ^PGEN)
 
-		/* Set Power State to D0 */
-		Store (3, Local0)
-		Store (Local0, ^D0D3)
-		Store (^D0D3, Local0)
+		/* Set Power State to D3 */
+		Or (PMCR, 0x0003, PMCR)
+		Store (PMCR, ^TEMP)
 	}
 }
 
@@ -110,12 +110,13 @@
 {
 	Name (_ADR, 0x001E0006)
 	Name (_DDN, "SD Controller")
+	Name (TEMP, 0)
 
 	OperationRegion (SDCR, PCI_Config, 0x00, 0x100)
-	Field (SDCR, DWordAcc, NoLock, Preserve)
+	Field (SDCR, WordAcc, NoLock, Preserve)
 	{
 		Offset (0x84),	/* PMECTRLSTATUS */
-		D0D3, 2,	/* POWERSTATE */
+		PMCR, 16,
 		Offset (0xa2),	/* PG_CONFIG */
 		, 2,
 		PGEN, 1,	/* PG_ENABLE */
@@ -138,14 +139,13 @@
 		^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A)
 		Sleep (2)
 
-		/* Set bits 31, 6, 2, 0 */
+		/* Set bits 8, 7, 2, 0 */
 		^^PCRO (PID_SCS, 0x600, 0x00000185)
 		Sleep (2)
 
 		/* Set Power State to D0 */
-		Store (Zero, Local0)
-		Store (Local0, ^D0D3)
-		Store (^D0D3, Local0)
+		And (PMCR, 0xFFFC, PMCR)
+		Store (PMCR, ^TEMP)
 	}
 
 	Method (_PS3, 0, Serialized)
@@ -153,10 +153,9 @@
 		/* Enable Power Gate */
 		Store (1, ^PGEN)
 
-		/* Set Power State to D0 */
-		Store (3, Local0)
-		Store (Local0, ^D0D3)
-		Store (^D0D3, Local0)
+		/* Set Power State to D3 */
+		Or (PMCR, 0x0003, PMCR)
+		Store (PMCR, ^TEMP)
 
 		/* Enable 20K pull-down on CLK, CMD and DAT lines */
 		^^PCRO (PID_GPIOCOM3, 0x4c4, 0x00001000)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b
Gerrit-Change-Number: 20364
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
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