<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20364">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: storage: Use word access for power state registers<br><br>In the D0 and D3 ACPI methods use word access to the PME status and<br>control register. This brings the code inline with the Intel reference<br>code and matches how the kernel handles access to this register.<br><br>BUG=b:35587084<br>BRANCH=eve<br>TEST=manual stress testing of D0<>D3 transition across multiple devices<br><br>Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b<br>Signed-off-by: Duncan Laurie <dlaurie@chromium.org><br>---<br>M src/soc/intel/skylake/acpi/scs.asl<br>1 file changed, 15 insertions(+), 16 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/20364/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl<br>index c2f50cc..240d2b8 100644<br>--- a/src/soc/intel/skylake/acpi/scs.asl<br>+++ b/src/soc/intel/skylake/acpi/scs.asl<br>@@ -21,12 +21,13 @@<br> Name (_ADR, 0x001E0004)<br> Name (_DDN, "eMMC Controller")<br> Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))<br>+ Name (TEMP, 0)<br> <br> OperationRegion (EMCR, PCI_Config, 0x00, 0x100)<br>- Field (EMCR, DWordAcc, NoLock, Preserve)<br>+ Field (EMCR, WordAcc, NoLock, Preserve)<br> {<br> Offset (0x84), /* PMECTRLSTATUS */<br>- D0D3, 2, /* POWERSTATE */<br>+ PMCR, 16,<br> Offset (0xa2), /* PG_CONFIG */<br> , 2,<br> PGEN, 1, /* PG_ENABLE */<br>@@ -98,10 +99,9 @@<br> /* Enable Power Gate */<br> Store (1, ^PGEN)<br> <br>- /* Set Power State to D0 */<br>- Store (3, Local0)<br>- Store (Local0, ^D0D3)<br>- Store (^D0D3, Local0)<br>+ /* Set Power State to D3 */<br>+ Or (PMCR, 0x0003, PMCR)<br>+ Store (PMCR, ^TEMP)<br> }<br> }<br> <br>@@ -110,12 +110,13 @@<br> {<br> Name (_ADR, 0x001E0006)<br> Name (_DDN, "SD Controller")<br>+ Name (TEMP, 0)<br> <br> OperationRegion (SDCR, PCI_Config, 0x00, 0x100)<br>- Field (SDCR, DWordAcc, NoLock, Preserve)<br>+ Field (SDCR, WordAcc, NoLock, Preserve)<br> {<br> Offset (0x84), /* PMECTRLSTATUS */<br>- D0D3, 2, /* POWERSTATE */<br>+ PMCR, 16,<br> Offset (0xa2), /* PG_CONFIG */<br> , 2,<br> PGEN, 1, /* PG_ENABLE */<br>@@ -138,14 +139,13 @@<br> ^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A)<br> Sleep (2)<br> <br>- /* Set bits 31, 6, 2, 0 */<br>+ /* Set bits 8, 7, 2, 0 */<br> ^^PCRO (PID_SCS, 0x600, 0x00000185)<br> Sleep (2)<br> <br> /* Set Power State to D0 */<br>- Store (Zero, Local0)<br>- Store (Local0, ^D0D3)<br>- Store (^D0D3, Local0)<br>+ And (PMCR, 0xFFFC, PMCR)<br>+ Store (PMCR, ^TEMP)<br> }<br> <br> Method (_PS3, 0, Serialized)<br>@@ -153,10 +153,9 @@<br> /* Enable Power Gate */<br> Store (1, ^PGEN)<br> <br>- /* Set Power State to D0 */<br>- Store (3, Local0)<br>- Store (Local0, ^D0D3)<br>- Store (^D0D3, Local0)<br>+ /* Set Power State to D3 */<br>+ Or (PMCR, 0x0003, PMCR)<br>+ Store (PMCR, ^TEMP)<br> <br> /* Enable 20K pull-down on CLK, CMD and DAT lines */<br> ^^PCRO (PID_GPIOCOM3, 0x4c4, 0x00001000)<br></pre><p>To view, visit <a href="https://review.coreboot.org/20364">change 20364</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20364"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b </div>
<div style="display:none"> Gerrit-Change-Number: 20364 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>