[coreboot-gerrit] Change in coreboot[master]: src/include: add IS_ENABLED() around Kconfig symbol references

Martin Roth (Code Review) gerrit at coreboot.org
Sun Jun 25 21:07:38 CEST 2017 

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20354


Change subject: src/include: add IS_ENABLED() around Kconfig symbol references
......................................................................

src/include: add IS_ENABLED() around Kconfig symbol references

Change-Id: I2fbe6376a1cf98d328464556917638a5679641d2
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/include/cpu/amd/car.h
M src/include/cpu/x86/lapic.h
M src/include/cpu/x86/post_code.h
M src/include/cpu/x86/smm.h
M src/include/cpu/x86/tsc.h
M src/include/device/device.h
M src/include/device/pci.h
M src/include/device/pci_ehci.h
M src/include/elog.h
M src/include/option.h
M src/include/pc80/mc146818rtc.h
M src/include/smp/atomic.h
M src/include/smp/node.h
M src/include/smp/spinlock.h
M src/include/stddef.h
M src/include/thread.h
M src/include/timestamp.h
M src/include/trace.h
M src/include/watchdog.h
19 files changed, 27 insertions(+), 27 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/20354/1

diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
index b4fbd60..47a9dfa 100644
--- a/src/include/cpu/amd/car.h
+++ b/src/include/cpu/amd/car.h
@@ -10,7 +10,7 @@
 void cache_as_ram_switch_stack(void *stacktop);
 void cache_as_ram_new_stack(void);
 
-#if CONFIG_CPU_AMD_AGESA || CONFIG_CPU_AMD_PI
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA) || IS_ENABLED(CONFIG_CPU_AMD_PI)
 void disable_cache_as_ram(void);
 #endif
 
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 6f3cbdb..e781b5a 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -7,7 +7,7 @@
 #include <smp/node.h>
 
 /* See if I need to initialize the local APIC */
-#if CONFIG_SMP || CONFIG_IOAPIC
+#if IS_ENABLED(CONFIG_SMP) || IS_ENABLED(CONFIG_IOAPIC)
 #  define NEED_LAPIC 1
 #else
 #  define NEED_LAPIC 0
@@ -54,7 +54,7 @@
 	return lapic_read(LAPIC_ID) >> 24;
 }
 
-#if !CONFIG_AP_IN_SIPI_WAIT
+#if !IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT)
 /* If we need to go back to sipi wait, we use the long non-inlined version of
  * this function in lapic_cpu_init.c
  */
@@ -149,7 +149,7 @@
 
 void setup_lapic(void);
 
-#if CONFIG_SMP
+#if IS_ENABLED(CONFIG_SMP)
 struct device;
 int start_cpu(struct device *cpu);
 #endif /* CONFIG_SMP */
diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h
index 6acfe10..cd3d159 100644
--- a/src/include/cpu/x86/post_code.h
+++ b/src/include/cpu/x86/post_code.h
@@ -2,7 +2,7 @@
 #include <console/post_codes.h>
 
 
-#if CONFIG_POST_IO
+#if IS_ENABLED(CONFIG_POST_IO)
 #define post_code(value)        \
 	movb    $value, %al;    \
 	outb    %al, $CONFIG_POST_IO_PORT
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 15e3ed3..41afd08 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -478,7 +478,7 @@
 
 void southbridge_smi_set_eos(void);
 
-#if CONFIG_SMM_TSEG
+#if IS_ENABLED(CONFIG_SMM_TSEG)
 void cpu_smi_handler(void);
 void northbridge_smi_handler(void);
 void southbridge_smi_handler(void);
@@ -493,7 +493,7 @@
 int  mainboard_smi_apmc(u8 data);
 void mainboard_smi_sleep(u8 slp_typ);
 
-#if !CONFIG_SMM_TSEG
+#if !IS_ENABLED(CONFIG_SMM_TSEG)
 void smi_release_lock(void);
 #endif
 
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 5a7fbc2..4cf4fbc 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -3,9 +3,9 @@
 
 #include <stdint.h>
 
-#if CONFIG_TSC_SYNC_MFENCE
+#if IS_ENABLED(CONFIG_TSC_SYNC_MFENCE)
 #define TSC_SYNC "mfence\n"
-#elif CONFIG_TSC_SYNC_LFENCE
+#elif IS_ENABLED(CONFIG_TSC_SYNC_LFENCE)
 #define TSC_SYNC "lfence\n"
 #else
 #define TSC_SYNC
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 5bc4d1c..242d297 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -53,7 +53,7 @@
 	void (*disable)(device_t dev);
 	void (*set_link)(device_t dev, unsigned int link);
 	void (*reset_bus)(struct bus *bus);
-#if CONFIG_GENERATE_SMBIOS_TABLES
+#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
 	int (*get_smbios_data)(device_t dev, int *handle,
 		unsigned long *current);
 	void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t);
@@ -163,7 +163,7 @@
 
 extern const char mainboard_name[];
 
-#if CONFIG_GFXUMA
+#if IS_ENABLED(CONFIG_GFXUMA)
 /* IGD UMA memory */
 extern uint64_t uma_memory_base;
 extern uint64_t uma_memory_size;
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 4f6dfbc..4283141 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -15,7 +15,7 @@
 #ifndef PCI_H
 #define PCI_H
 
-#if CONFIG_PCI
+#if IS_ENABLED(CONFIG_PCI)
 
 #include <stdint.h>
 #include <stddef.h>
diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h
index 1eb3cd0..48178c8 100644
--- a/src/include/device/pci_ehci.h
+++ b/src/include/device/pci_ehci.h
@@ -29,7 +29,7 @@
 void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base);
 
 #ifndef __PRE_RAM__
-#if !CONFIG_USBDEBUG
+#if !IS_ENABLED(CONFIG_USBDEBUG)
 #define pci_ehci_read_resources pci_dev_read_resources
 #else
 /* Relocation of EHCI Debug Port BAR
diff --git a/src/include/elog.h b/src/include/elog.h
index ecda87d..f6f0bdd 100644
--- a/src/include/elog.h
+++ b/src/include/elog.h
@@ -206,7 +206,7 @@
 /* Deep Sx wake variant */
 #define ELOG_TYPE_ACPI_DEEP_WAKE          0xad
 
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
 /* Eventlog backing storage must be initialized before calling elog_init(). */
 extern int elog_init(void);
 extern int elog_clear(void);
diff --git a/src/include/option.h b/src/include/option.h
index 83f3a84..f6ede96 100644
--- a/src/include/option.h
+++ b/src/include/option.h
@@ -6,7 +6,7 @@
  * storage can be used. This will benefit machines without CMOS as well as those
  * without a battery-backed CMOS (e.g. some laptops).
  */
-#if CONFIG_USE_OPTION_TABLE
+#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
 #include <pc80/mc146818rtc.h>
 #else
 #include <types.h>
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index ec0bf8e..f6a1c04 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -1,7 +1,7 @@
 #ifndef PC80_MC146818RTC_H
 #define PC80_MC146818RTC_H
 
-#if CONFIG_ARCH_X86
+#if IS_ENABLED(CONFIG_ARCH_X86)
 
 #include <arch/io.h>
 #include <types.h>
@@ -193,8 +193,8 @@
 #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, \
 	CMOS_VLEN_ ##name, (default))
 
-#if CONFIG_CMOS_POST
-#if CONFIG_USE_OPTION_TABLE
+#if IS_ENABLED(CONFIG_CMOS_POST)
+#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
 # include "option_table.h"
 # define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3)
 #else
@@ -241,7 +241,7 @@
 		/* Initialize to zero */
 		cmos_write(0, CMOS_POST_BANK_0_OFFSET);
 		cmos_write(0, CMOS_POST_BANK_1_OFFSET);
-#if CONFIG_CMOS_POST_EXTRA
+#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
 		cmos_write32(CMOS_POST_BANK_0_EXTRA, 0);
 		cmos_write32(CMOS_POST_BANK_1_EXTRA, 0);
 #endif
diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h
index 56df9f5..5db59e9 100644
--- a/src/include/smp/atomic.h
+++ b/src/include/smp/atomic.h
@@ -1,7 +1,7 @@
 #ifndef SMP_ATOMIC_H
 #define SMP_ATOMIC_H
 
-#if CONFIG_SMP
+#if IS_ENABLED(CONFIG_SMP)
 #include <arch/smp/atomic.h>
 #else
 
diff --git a/src/include/smp/node.h b/src/include/smp/node.h
index 4e45c46..65931bc 100644
--- a/src/include/smp/node.h
+++ b/src/include/smp/node.h
@@ -1,7 +1,7 @@
 #ifndef _SMP_NODE_H_
 #define _SMP_NODE_H_
 
-#if CONFIG_SMP
+#if IS_ENABLED(CONFIG_SMP)
 int boot_cpu(void);
 #else
 #define boot_cpu(x) 1
diff --git a/src/include/smp/spinlock.h b/src/include/smp/spinlock.h
index f181f45..a7b8001 100644
--- a/src/include/smp/spinlock.h
+++ b/src/include/smp/spinlock.h
@@ -1,7 +1,7 @@
 #ifndef SMP_SPINLOCK_H
 #define SMP_SPINLOCK_H
 
-#if CONFIG_SMP
+#if IS_ENABLED(CONFIG_SMP)
 #include <arch/smp/spinlock.h>
 #else /* !CONFIG_SMP */
 
diff --git a/src/include/stddef.h b/src/include/stddef.h
index af63196..5df7735 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -37,7 +37,7 @@
 #endif
 
 /* Work around non-writable data segment in execute-in-place romstage on x86. */
-#if defined(__PRE_RAM__) && CONFIG_ARCH_X86
+#if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_ARCH_X86)
 #define MAYBE_STATIC
 #else
 #define MAYBE_STATIC static
diff --git a/src/include/thread.h b/src/include/thread.h
index 586fb3a..ed04beb 100644
--- a/src/include/thread.h
+++ b/src/include/thread.h
@@ -21,7 +21,7 @@
 #include <timer.h>
 #include <arch/cpu.h>
 
-#if CONFIG_COOP_MULTITASKING && !defined(__SMM__) && !defined(__PRE_RAM__)
+#if IS_ENABLED(CONFIG_COOP_MULTITASKING) && !defined(__SMM__) && !defined(__PRE_RAM__)
 
 struct thread {
 	int id;
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index 58edb52..d073529 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -18,7 +18,7 @@
 
 #include <commonlib/timestamp_serialized.h>
 
-#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT \
+#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) \
 	|| !defined(__PRE_RAM__))
 /*
  * timestamp_init() needs to be called once for each of these cases:
diff --git a/src/include/trace.h b/src/include/trace.h
index 8745966..12c7fa6 100644
--- a/src/include/trace.h
+++ b/src/include/trace.h
@@ -25,7 +25,7 @@
 
 #else /* !__PRE_RAM__ */
 
-#if CONFIG_TRACE && !defined(__SMM__)
+#if IS_ENABLED(CONFIG_TRACE) && !defined(__SMM__)
 
 void __cyg_profile_func_enter(void *, void *)
 				 __attribute__ ((no_instrument_function));
diff --git a/src/include/watchdog.h b/src/include/watchdog.h
index 375563d..e8de580 100644
--- a/src/include/watchdog.h
+++ b/src/include/watchdog.h
@@ -1,7 +1,7 @@
 #ifndef WATCHDOG_H
 #define WATCHDOG_H
 
-#if CONFIG_USE_WATCHDOG_ON_BOOT
+#if IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)
 void watchdog_off(void);
 #else
 #define watchdog_off() { while (0); }

-- 
To view, visit https://review.coreboot.org/20354
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2fbe6376a1cf98d328464556917638a5679641d2
Gerrit-Change-Number: 20354
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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