[coreboot-gerrit] Change in coreboot[master]: src/southbridge: add IS_ENABLED() around Kconfig symbol refe...

Martin Roth (Code Review) gerrit at coreboot.org
Sun Jun 25 21:07:33 CEST 2017 

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20353


Change subject: src/southbridge: add IS_ENABLED() around Kconfig symbol references
......................................................................

src/southbridge: add IS_ENABLED() around Kconfig symbol references

Change-Id: Ie965cbcf7f7b6f6c9e9a69e2a1ff0ba491246cbe
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/southbridge/nvidia/ck804/early_setup.c
M src/southbridge/nvidia/ck804/early_setup_car.c
M src/southbridge/nvidia/mcp55/early_setup_car.c
M src/southbridge/nvidia/mcp55/smbus.c
M src/southbridge/via/k8t890/bridge.c
M src/southbridge/via/k8t890/ctrl.c
M src/southbridge/via/k8t890/dram.c
M src/southbridge/via/k8t890/early_car.c
M src/southbridge/via/k8t890/romstrap.S
M src/southbridge/via/vt8237r/ide.c
M src/southbridge/via/vt8237r/lpc.c
M src/southbridge/via/vt8237r/nic.c
M src/southbridge/via/vt8237r/pirq.c
M src/southbridge/via/vt8237r/usb.c
M src/southbridge/via/vt8237r/vt8237r.h
15 files changed, 55 insertions(+), 52 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/20353/1

diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c
index 79c9eff..673c44d 100644
--- a/src/southbridge/nvidia/ck804/early_setup.c
+++ b/src/southbridge/nvidia/ck804/early_setup.c
@@ -250,7 +250,7 @@
 
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
-#if CONFIG_CK804_USE_NIC
+#if IS_ENABLED(CONFIG_CK804_USE_NIC)
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
@@ -258,7 +258,7 @@
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23),
 #endif
 
-#if CONFIG_CK804_USE_ACI
+#if IS_ENABLED(CONFIG_CK804_USE_ACI)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
 #endif
@@ -268,7 +268,7 @@
 #endif
 
 #if CONFIG_CK804_NUM > 1
-#if CONFIG_CK804_USE_NIC
+#if IS_ENABLED(CONFIG_CK804_USE_NIC)
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
 	RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
 	RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3,  ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index aeea41b..6472abf 100644
--- a/src/southbridge/nvidia/ck804/early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
@@ -198,7 +198,7 @@
 		/* SYSCTRL */
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
-#if CONFIG_CK804_USE_NIC
+#if IS_ENABLED(CONFIG_CK804_USE_NIC)
 		RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
@@ -206,7 +206,7 @@
 		RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23),
 #endif
 
-#if CONFIG_CK804_USE_ACI
+#if IS_ENABLED(CONFIG_CK804_USE_ACI)
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
 #endif
@@ -280,7 +280,7 @@
 
 		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8),
 
-#if CONFIG_CK804_USE_NIC
+#if IS_ENABLED(CONFIG_CK804_USE_NIC)
 		RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c
index 7f1d03b..8019a8e 100644
--- a/src/southbridge/nvidia/mcp55/early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c
@@ -250,7 +250,7 @@
 	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
 #endif
 
-#if CONFIG_MCP55_USE_AZA
+#if IS_ENABLED(CONFIG_MCP55_USE_AZA)
 	RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
 
 #endif
@@ -260,7 +260,7 @@
 	MCP55_MB_SETUP
 #endif
 
-#if CONFIG_MCP55_USE_AZA
+#if IS_ENABLED(CONFIG_MCP55_USE_AZA)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3 << 2), (2 << 2),
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2),
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2),
@@ -284,7 +284,7 @@
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
 
-#if CONFIG_MCP55_USE_NIC
+#if IS_ENABLED(CONFIG_MCP55_USE_NIC)
 	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20),
 
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c
index 7829a28..c41445b 100644
--- a/src/southbridge/nvidia/mcp55/smbus.c
+++ b/src/southbridge/nvidia/mcp55/smbus.c
@@ -89,7 +89,7 @@
 	.write_byte	= lsmbus_write_byte,
 };
 
-#if CONFIG_HAVE_ACPI_TABLES
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 unsigned pm_base;
 #endif
 
@@ -108,7 +108,7 @@
 
 static void mcp55_sm_init(device_t dev)
 {
-#if CONFIG_HAVE_ACPI_TABLES
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 	struct resource *res;
 
 	res = find_resource(dev, 0x60);
diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c
index e1b6bfe..f7ccd75 100644
--- a/src/southbridge/via/k8t890/bridge.c
+++ b/src/southbridge/via/k8t890/bridge.c
@@ -29,7 +29,7 @@
 	writeback(dev, 0x40, 0x91);
 	writeback(dev, 0x41, 0x40);
 	writeback(dev, 0x43, 0x44);
-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
 	writeback(dev, 0x42, 0x80);
 	writeback(dev, 0x44, 0x35);
 #else
@@ -45,7 +45,7 @@
 	 * (Forward VGA compatible memory and I/O cycles )
 	 */
 
-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
 	writeback(dev, 0x3e, 0x0a);
 #else
 	writeback(dev, 0x3e, 0x16);
diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c
index 7255a92..f5e248d 100644
--- a/src/southbridge/via/k8t890/ctrl.c
+++ b/src/southbridge/via/k8t890/ctrl.c
@@ -47,11 +47,11 @@
 	pci_write_config8(dev, 0x70, 0xc2);
 
 	/* PCI Control */
-#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
 	pci_write_config8(dev, 0x72, 0xee);
 #endif
 	pci_write_config8(dev, 0x73, 0x01);
-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
 	pci_write_config8(dev, 0x74, 0x64);
 	pci_write_config8(dev, 0x75, 0x3f);
 #else
@@ -59,7 +59,7 @@
 	pci_write_config8(dev, 0x75, 0x0f);
 #endif
 	pci_write_config8(dev, 0x76, 0x50);
-#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
 	pci_write_config8(dev, 0x77, 0x08);
 #endif
 	pci_write_config8(dev, 0x78, 0x01);
@@ -156,7 +156,7 @@
 	/* PCI CFG Address bits[27:24] are used as extended register address
 	   bit[11:8] */
 
-#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
 	pci_write_config8(dev, 0x47, 0x30);
 #endif
 
diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c
index e907528..1f126cc 100644
--- a/src/southbridge/via/k8t890/dram.c
+++ b/src/southbridge/via/k8t890/dram.c
@@ -69,7 +69,7 @@
 
 static void dram_enable_k8m890(struct device *dev)
 {
-#if CONFIG_GFXUMA
+#if IS_ENABLED(CONFIG_GFXUMA)
 	msr_t msr;
 	int ret;
 	unsigned int fbbits;
@@ -121,7 +121,7 @@
 
 static void dram_init_fb(struct device *dev)
 {
-#if CONFIG_GFXUMA
+#if IS_ENABLED(CONFIG_GFXUMA)
 	/* Important bits:
 	 * Enable the internal GFX bit 7 of reg 0xa1 plus in same reg:
 	 * bits 6:4 X fbuffer size will be  2^(X+2) or 100 = 64MB, 101 = 128MB
diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c
index 5f1e4c4..64f0425 100644
--- a/src/southbridge/via/k8t890/early_car.c
+++ b/src/southbridge/via/k8t890/early_car.c
@@ -32,7 +32,7 @@
 /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */
 static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
 
-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
 #define K8X8XX_HT_CFG_BASE 0xc0
 #else
 #define K8X8XX_HT_CFG_BASE 0x60
@@ -50,7 +50,7 @@
 	u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width;
 	u16 vldtcaps;
 
-#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
 	u8 reg;
 
 	/* hack, enable NVRAM in chipset */
@@ -76,21 +76,21 @@
 		ldtnr = 2;
 	}
 
-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800)
 	printk(BIOS_DEBUG, "K8M800 found at LDT ");
-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800)
 	printk(BIOS_DEBUG, "K8T800 found at LDT ");
-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
 	printk(BIOS_DEBUG, "K8T800_OLD found at LDT ");
 	pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00);
 	pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50);
-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO)
 	printk(BIOS_DEBUG, "K8T800 Pro found at LDT ");
-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890)
 	printk(BIOS_DEBUG, "K8M890 found at LDT ");
 	/* K8M890 fix HT delay */
 	pci_write_config8(PCI_DEV(0, 0x0, 2), 0xab, 0x22);
-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890)
 	printk(BIOS_DEBUG, "K8T890 found at LDT ");
 #endif
 	printk(BIOS_DEBUG, "%02x", ldtnr);
diff --git a/src/southbridge/via/k8t890/romstrap.S b/src/southbridge/via/k8t890/romstrap.S
index 2115eaa..cb384e9 100644
--- a/src/southbridge/via/k8t890/romstrap.S
+++ b/src/southbridge/via/k8t890/romstrap.S
@@ -29,7 +29,9 @@
  * Below are some Dev0 Func2 HT control registers values,
  * depending on strap pin, one of below lines is used.
  */
-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800) || \
+	IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800) || \
+	IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
 
 tblpointer:
 .long 0x50220000, 0X619707C2
@@ -48,7 +50,7 @@
 .long 0x0
 .long 0x0
 
-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890)
 
 tblpointer:
 .long 0x504400FF, 0x61970FC2	//;200M
@@ -68,7 +70,7 @@
 .long 0x0
 
 
-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890)
 
 tblpointer:
 .long 0x504400AA, 0x61970FC2	//;200M
diff --git a/src/southbridge/via/vt8237r/ide.c b/src/southbridge/via/vt8237r/ide.c
index 8550d46..4579171 100644
--- a/src/southbridge/via/vt8237r/ide.c
+++ b/src/southbridge/via/vt8237r/ide.c
@@ -101,7 +101,7 @@
 	cablesel |= vt8237_ide_80pin_detect(dev);
 	pci_write_config32(dev, IDE_UDMA, cablesel);
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	device_t lpc_dev;
 
 	/* Set PATA Output Drive Strength */
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 9d91749..70ac5d9 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -34,7 +34,7 @@
 
 static void southbridge_init_common(struct device *dev);
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
                    /* Interrupts for  INT# A   B   C   D */
 static const unsigned char pciIrqs[4]  = { 10, 11, 12, 0};
 
@@ -61,7 +61,7 @@
 /** Set up PCI IRQ routing, route everything through APIC. */
 static void pci_routing_fixup(struct device *dev)
 {
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	device_t pdev;
 #endif
 
@@ -74,7 +74,7 @@
 	/* Gate Interrupts until RAM Writes are flushed */
 	pci_write_config8(dev, 0x49, 0x20);
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 
 	/* Share INTE-INTH with INTA-INTD as per stock BIOS. */
 	pci_write_config8(dev, 0x46, 0x00);
@@ -160,7 +160,7 @@
 	/* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */
 	pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ);
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	/* Primary interrupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
 	pci_write_config16(dev, 0x84, 0x3052);
 #else
@@ -195,7 +195,7 @@
 	 * 0 = USB Wakeup
 	 */
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	pci_write_config8(dev, 0x95, 0xc2);
 #else
 	tmp = 0xcc;
@@ -263,7 +263,7 @@
 
 	cfg = dev->chip_info;
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");
 	/*
 	 * TODO: Looks like stock BIOS can do this but causes a hang
@@ -313,14 +313,15 @@
 	enables |= 0x08;
 	pci_write_config8(dev, 0x4f, enables);
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	/*
 	 * Set Read Pass Write Control Enable
 	 */
 	pci_write_config8(dev, 0x48, 0x0c);
 #else
 
-  #if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
+  #if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800) || \
+	IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)
 	/* It seems that when we pair with the K8T800, we need to disable
 	 * the A2 mask
 	 */
@@ -337,7 +338,7 @@
 
 	southbridge_init_common(dev);
 
-#if !CONFIG_EPIA_VT8237R_INIT
+#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	/* FIXME: Intel needs more bit set for C2/C3. */
 
 	/*
@@ -444,7 +445,7 @@
 {
 	u8 enables, byte;
 	struct southbridge_via_vt8237r_config *cfg;
-#if !CONFIG_EPIA_VT8237R_INIT
+#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	unsigned char pwr_on;
 #endif
 
@@ -456,7 +457,7 @@
 	pci_write_config8(dev, PCI_COMMAND, byte);
 
 /* EPIA-N(L) Uses CN400 for BIOS Access */
-#if !CONFIG_EPIA_VT8237R_INIT
+#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	/* Enable the internal I/O decode. */
 	enables = pci_read_config8(dev, 0x6C);
 	enables |= 0x80;
@@ -495,7 +496,7 @@
 	/* Delay transaction control */
 	pci_write_config8(dev, 0x43, 0xb);
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	/* I/O recovery time, default IDE routing */
 	pci_write_config8(dev, 0x4c, 0x04);
 
@@ -555,7 +556,7 @@
 	/* Enable serial IRQ, 6PCI clocks. */
 	pci_write_config8(dev, 0x52, 0x9);
 #endif
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
 	smm_lock();
 #endif
 
diff --git a/src/southbridge/via/vt8237r/nic.c b/src/southbridge/via/vt8237r/nic.c
index ebebd37..aa60489 100644
--- a/src/southbridge/via/vt8237r/nic.c
+++ b/src/southbridge/via/vt8237r/nic.c
@@ -23,7 +23,7 @@
 
 static void vt8237_eth_read_resources(struct device *dev)
 {
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	struct resource *res;
 
 	/* Fix the I/O Resources of the USB2.0 Interface */
diff --git a/src/southbridge/via/vt8237r/pirq.c b/src/southbridge/via/vt8237r/pirq.c
index ec393b4..fd55b1f 100644
--- a/src/southbridge/via/vt8237r/pirq.c
+++ b/src/southbridge/via/vt8237r/pirq.c
@@ -21,7 +21,7 @@
 #include <device/pci_ids.h>
 #include <pc80/i8259.h>
 
-#if (CONFIG_PIRQ_ROUTE == 1 && CONFIG_GENERATE_PIRQ_TABLE == 1)
+#if IS_ENABLED(CONFIG_PIRQ_ROUTE) && IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)
 void pirq_assign_irqs(const unsigned char route[4])
 {
 	device_t pdev;
diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c
index 42da53a..057a07d 100644
--- a/src/southbridge/via/vt8237r/usb.c
+++ b/src/southbridge/via/vt8237r/usb.c
@@ -21,13 +21,13 @@
 #include "chip.h"
 #include "vt8237r.h"
 
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800};
 #endif
 
 static void usb_i_init(struct device *dev)
 {
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	u8 reg8;
 
 	printk(BIOS_DEBUG, "Entering %s\n", __func__);
@@ -66,7 +66,7 @@
 
 static void vt8237_usb_i_read_resources(struct device *dev)
 {
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	struct resource *res;
 	u8 function = (u8) dev->path.pci.devfn & 0x7;
 
@@ -92,7 +92,7 @@
 static void usb_ii_init(struct device *dev)
 {
 	struct southbridge_via_vt8237r_config *cfg;
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	u8 reg8;
 
 	printk(BIOS_DEBUG, "Entering %s\n", __func__);
@@ -136,7 +136,7 @@
 
 static void vt8237_usb_ii_read_resources(struct device *dev)
 {
-#if CONFIG_EPIA_VT8237R_INIT
+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)
 	struct resource *res;
 
 	/* Fix the I/O Resources of the USB2.0 Interface */
diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h
index 95f9750..f58b691 100644
--- a/src/southbridge/via/vt8237r/vt8237r.h
+++ b/src/southbridge/via/vt8237r/vt8237r.h
@@ -89,7 +89,7 @@
 #define I2C_TRANS_CMD			0x40
 #define CLOCK_SLAVE_ADDRESS		0x69
 
-#if CONFIG_DEBUG_SMBUS
+#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
 #define PRINT_DEBUG(x)		printk(BIOS_DEBUG, x)
 #define PRINT_DEBUG_HEX16(x)	printk(BIOS_DEBUG, "%04x", x)
 #else

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie965cbcf7f7b6f6c9e9a69e2a1ff0ba491246cbe
Gerrit-Change-Number: 20353
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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