<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20353">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/southbridge: add IS_ENABLED() around Kconfig symbol references<br><br>Change-Id: Ie965cbcf7f7b6f6c9e9a69e2a1ff0ba491246cbe<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/southbridge/nvidia/ck804/early_setup.c<br>M src/southbridge/nvidia/ck804/early_setup_car.c<br>M src/southbridge/nvidia/mcp55/early_setup_car.c<br>M src/southbridge/nvidia/mcp55/smbus.c<br>M src/southbridge/via/k8t890/bridge.c<br>M src/southbridge/via/k8t890/ctrl.c<br>M src/southbridge/via/k8t890/dram.c<br>M src/southbridge/via/k8t890/early_car.c<br>M src/southbridge/via/k8t890/romstrap.S<br>M src/southbridge/via/vt8237r/ide.c<br>M src/southbridge/via/vt8237r/lpc.c<br>M src/southbridge/via/vt8237r/nic.c<br>M src/southbridge/via/vt8237r/pirq.c<br>M src/southbridge/via/vt8237r/usb.c<br>M src/southbridge/via/vt8237r/vt8237r.h<br>15 files changed, 55 insertions(+), 52 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/20353/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c<br>index 79c9eff..673c44d 100644<br>--- a/src/southbridge/nvidia/ck804/early_setup.c<br>+++ b/src/southbridge/nvidia/ck804/early_setup.c<br>@@ -250,7 +250,7 @@<br> <br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),<br>-#if CONFIG_CK804_USE_NIC<br>+#if IS_ENABLED(CONFIG_CK804_USE_NIC)<br> RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),<br>@@ -258,7 +258,7 @@<br> RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23),<br> #endif<br> <br>-#if CONFIG_CK804_USE_ACI<br>+#if IS_ENABLED(CONFIG_CK804_USE_ACI)<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),<br> #endif<br>@@ -268,7 +268,7 @@<br> #endif<br> <br> #if CONFIG_CK804_NUM > 1<br>-#if CONFIG_CK804_USE_NIC<br>+#if IS_ENABLED(CONFIG_CK804_USE_NIC)<br> RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,<br> RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),<br> RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),<br>diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c<br>index aeea41b..6472abf 100644<br>--- a/src/southbridge/nvidia/ck804/early_setup_car.c<br>+++ b/src/southbridge/nvidia/ck804/early_setup_car.c<br>@@ -198,7 +198,7 @@<br> /* SYSCTRL */<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),<br>-#if CONFIG_CK804_USE_NIC<br>+#if IS_ENABLED(CONFIG_CK804_USE_NIC)<br> RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),<br>@@ -206,7 +206,7 @@<br> RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23),<br> #endif<br> <br>-#if CONFIG_CK804_USE_ACI<br>+#if IS_ENABLED(CONFIG_CK804_USE_ACI)<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),<br> #endif<br>@@ -280,7 +280,7 @@<br> <br> RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8),<br> <br>-#if CONFIG_CK804_USE_NIC<br>+#if IS_ENABLED(CONFIG_CK804_USE_NIC)<br> RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),<br>diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c<br>index 7f1d03b..8019a8e 100644<br>--- a/src/southbridge/nvidia/mcp55/early_setup_car.c<br>+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c<br>@@ -250,7 +250,7 @@<br> RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,<br> #endif<br> <br>-#if CONFIG_MCP55_USE_AZA<br>+#if IS_ENABLED(CONFIG_MCP55_USE_AZA)<br> RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,<br> <br> #endif<br>@@ -260,7 +260,7 @@<br> MCP55_MB_SETUP<br> #endif<br> <br>-#if CONFIG_MCP55_USE_AZA<br>+#if IS_ENABLED(CONFIG_MCP55_USE_AZA)<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3 << 2), (2 << 2),<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2),<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2),<br>@@ -284,7 +284,7 @@<br> <br> RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,<br> <br>-#if CONFIG_MCP55_USE_NIC<br>+#if IS_ENABLED(CONFIG_MCP55_USE_NIC)<br> RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20),<br> <br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),<br>diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c<br>index 7829a28..c41445b 100644<br>--- a/src/southbridge/nvidia/mcp55/smbus.c<br>+++ b/src/southbridge/nvidia/mcp55/smbus.c<br>@@ -89,7 +89,7 @@<br> .write_byte = lsmbus_write_byte,<br> };<br> <br>-#if CONFIG_HAVE_ACPI_TABLES<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)<br> unsigned pm_base;<br> #endif<br> <br>@@ -108,7 +108,7 @@<br> <br> static void mcp55_sm_init(device_t dev)<br> {<br>-#if CONFIG_HAVE_ACPI_TABLES<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)<br> struct resource *res;<br> <br> res = find_resource(dev, 0x60);<br>diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c<br>index e1b6bfe..f7ccd75 100644<br>--- a/src/southbridge/via/k8t890/bridge.c<br>+++ b/src/southbridge/via/k8t890/bridge.c<br>@@ -29,7 +29,7 @@<br> writeback(dev, 0x40, 0x91);<br> writeback(dev, 0x41, 0x40);<br> writeback(dev, 0x43, 0x44);<br>-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)<br> writeback(dev, 0x42, 0x80);<br> writeback(dev, 0x44, 0x35);<br> #else<br>@@ -45,7 +45,7 @@<br> * (Forward VGA compatible memory and I/O cycles )<br> */<br> <br>-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)<br> writeback(dev, 0x3e, 0x0a);<br> #else<br> writeback(dev, 0x3e, 0x16);<br>diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c<br>index 7255a92..f5e248d 100644<br>--- a/src/southbridge/via/k8t890/ctrl.c<br>+++ b/src/southbridge/via/k8t890/ctrl.c<br>@@ -47,11 +47,11 @@<br> pci_write_config8(dev, 0x70, 0xc2);<br> <br> /* PCI Control */<br>-#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD<br>+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)<br> pci_write_config8(dev, 0x72, 0xee);<br> #endif<br> pci_write_config8(dev, 0x73, 0x01);<br>-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)<br> pci_write_config8(dev, 0x74, 0x64);<br> pci_write_config8(dev, 0x75, 0x3f);<br> #else<br>@@ -59,7 +59,7 @@<br> pci_write_config8(dev, 0x75, 0x0f);<br> #endif<br> pci_write_config8(dev, 0x76, 0x50);<br>-#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD<br>+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)<br> pci_write_config8(dev, 0x77, 0x08);<br> #endif<br> pci_write_config8(dev, 0x78, 0x01);<br>@@ -156,7 +156,7 @@<br> /* PCI CFG Address bits[27:24] are used as extended register address<br> bit[11:8] */<br> <br>-#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD<br>+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)<br> pci_write_config8(dev, 0x47, 0x30);<br> #endif<br> <br>diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c<br>index e907528..1f126cc 100644<br>--- a/src/southbridge/via/k8t890/dram.c<br>+++ b/src/southbridge/via/k8t890/dram.c<br>@@ -69,7 +69,7 @@<br> <br> static void dram_enable_k8m890(struct device *dev)<br> {<br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> msr_t msr;<br> int ret;<br> unsigned int fbbits;<br>@@ -121,7 +121,7 @@<br> <br> static void dram_init_fb(struct device *dev)<br> {<br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> /* Important bits:<br> * Enable the internal GFX bit 7 of reg 0xa1 plus in same reg:<br> * bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB<br>diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c<br>index 5f1e4c4..64f0425 100644<br>--- a/src/southbridge/via/k8t890/early_car.c<br>+++ b/src/southbridge/via/k8t890/early_car.c<br>@@ -32,7 +32,7 @@<br> /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */<br> static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};<br> <br>-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)<br> #define K8X8XX_HT_CFG_BASE 0xc0<br> #else<br> #define K8X8XX_HT_CFG_BASE 0x60<br>@@ -50,7 +50,7 @@<br> u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width;<br> u16 vldtcaps;<br> <br>-#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD<br>+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)<br> u8 reg;<br> <br> /* hack, enable NVRAM in chipset */<br>@@ -76,21 +76,21 @@<br> ldtnr = 2;<br> }<br> <br>-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800)<br> printk(BIOS_DEBUG, "K8M800 found at LDT ");<br>-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800<br>+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800)<br> printk(BIOS_DEBUG, "K8T800 found at LDT ");<br>-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD<br>+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)<br> printk(BIOS_DEBUG, "K8T800_OLD found at LDT ");<br> pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00);<br> pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50);<br>-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO<br>+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO)<br> printk(BIOS_DEBUG, "K8T800 Pro found at LDT ");<br>-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890<br>+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890)<br> printk(BIOS_DEBUG, "K8M890 found at LDT ");<br> /* K8M890 fix HT delay */<br> pci_write_config8(PCI_DEV(0, 0x0, 2), 0xab, 0x22);<br>-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890<br>+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890)<br> printk(BIOS_DEBUG, "K8T890 found at LDT ");<br> #endif<br> printk(BIOS_DEBUG, "%02x", ldtnr);<br>diff --git a/src/southbridge/via/k8t890/romstrap.S b/src/southbridge/via/k8t890/romstrap.S<br>index 2115eaa..cb384e9 100644<br>--- a/src/southbridge/via/k8t890/romstrap.S<br>+++ b/src/southbridge/via/k8t890/romstrap.S<br>@@ -29,7 +29,9 @@<br> * Below are some Dev0 Func2 HT control registers values,<br> * depending on strap pin, one of below lines is used.<br> */<br>-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800) || \<br>+ IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800) || \<br>+ IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)<br> <br> tblpointer:<br> .long 0x50220000, 0X619707C2<br>@@ -48,7 +50,7 @@<br> .long 0x0<br> .long 0x0<br> <br>-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890<br>+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890)<br> <br> tblpointer:<br> .long 0x504400FF, 0x61970FC2 //;200M<br>@@ -68,7 +70,7 @@<br> .long 0x0<br> <br> <br>-#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890<br>+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890)<br> <br> tblpointer:<br> .long 0x504400AA, 0x61970FC2 //;200M<br>diff --git a/src/southbridge/via/vt8237r/ide.c b/src/southbridge/via/vt8237r/ide.c<br>index 8550d46..4579171 100644<br>--- a/src/southbridge/via/vt8237r/ide.c<br>+++ b/src/southbridge/via/vt8237r/ide.c<br>@@ -101,7 +101,7 @@<br> cablesel |= vt8237_ide_80pin_detect(dev);<br> pci_write_config32(dev, IDE_UDMA, cablesel);<br> <br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> device_t lpc_dev;<br> <br> /* Set PATA Output Drive Strength */<br>diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c<br>index 9d91749..70ac5d9 100644<br>--- a/src/southbridge/via/vt8237r/lpc.c<br>+++ b/src/southbridge/via/vt8237r/lpc.c<br>@@ -34,7 +34,7 @@<br> <br> static void southbridge_init_common(struct device *dev);<br> <br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> /* Interrupts for INT# A B C D */<br> static const unsigned char pciIrqs[4] = { 10, 11, 12, 0};<br> <br>@@ -61,7 +61,7 @@<br> /** Set up PCI IRQ routing, route everything through APIC. */<br> static void pci_routing_fixup(struct device *dev)<br> {<br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> device_t pdev;<br> #endif<br> <br>@@ -74,7 +74,7 @@<br> /* Gate Interrupts until RAM Writes are flushed */<br> pci_write_config8(dev, 0x49, 0x20);<br> <br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> <br> /* Share INTE-INTH with INTA-INTD as per stock BIOS. */<br> pci_write_config8(dev, 0x46, 0x00);<br>@@ -160,7 +160,7 @@<br> /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */<br> pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ);<br> <br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> /* Primary interrupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */<br> pci_write_config16(dev, 0x84, 0x3052);<br> #else<br>@@ -195,7 +195,7 @@<br> * 0 = USB Wakeup<br> */<br> <br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> pci_write_config8(dev, 0x95, 0xc2);<br> #else<br> tmp = 0xcc;<br>@@ -263,7 +263,7 @@<br> <br> cfg = dev->chip_info;<br> <br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");<br> /*<br> * TODO: Looks like stock BIOS can do this but causes a hang<br>@@ -313,14 +313,15 @@<br> enables |= 0x08;<br> pci_write_config8(dev, 0x4f, enables);<br> <br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> /*<br> * Set Read Pass Write Control Enable<br> */<br> pci_write_config8(dev, 0x48, 0x0c);<br> #else<br> <br>- #if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD<br>+ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800) || \<br>+ IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD)<br> /* It seems that when we pair with the K8T800, we need to disable<br> * the A2 mask<br> */<br>@@ -337,7 +338,7 @@<br> <br> southbridge_init_common(dev);<br> <br>-#if !CONFIG_EPIA_VT8237R_INIT<br>+#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> /* FIXME: Intel needs more bit set for C2/C3. */<br> <br> /*<br>@@ -444,7 +445,7 @@<br> {<br> u8 enables, byte;<br> struct southbridge_via_vt8237r_config *cfg;<br>-#if !CONFIG_EPIA_VT8237R_INIT<br>+#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> unsigned char pwr_on;<br> #endif<br> <br>@@ -456,7 +457,7 @@<br> pci_write_config8(dev, PCI_COMMAND, byte);<br> <br> /* EPIA-N(L) Uses CN400 for BIOS Access */<br>-#if !CONFIG_EPIA_VT8237R_INIT<br>+#if !IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> /* Enable the internal I/O decode. */<br> enables = pci_read_config8(dev, 0x6C);<br> enables |= 0x80;<br>@@ -495,7 +496,7 @@<br> /* Delay transaction control */<br> pci_write_config8(dev, 0x43, 0xb);<br> <br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> /* I/O recovery time, default IDE routing */<br> pci_write_config8(dev, 0x4c, 0x04);<br> <br>@@ -555,7 +556,7 @@<br> /* Enable serial IRQ, 6PCI clocks. */<br> pci_write_config8(dev, 0x52, 0x9);<br> #endif<br>-#if CONFIG_HAVE_SMI_HANDLER<br>+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br> smm_lock();<br> #endif<br> <br>diff --git a/src/southbridge/via/vt8237r/nic.c b/src/southbridge/via/vt8237r/nic.c<br>index ebebd37..aa60489 100644<br>--- a/src/southbridge/via/vt8237r/nic.c<br>+++ b/src/southbridge/via/vt8237r/nic.c<br>@@ -23,7 +23,7 @@<br> <br> static void vt8237_eth_read_resources(struct device *dev)<br> {<br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> struct resource *res;<br> <br> /* Fix the I/O Resources of the USB2.0 Interface */<br>diff --git a/src/southbridge/via/vt8237r/pirq.c b/src/southbridge/via/vt8237r/pirq.c<br>index ec393b4..fd55b1f 100644<br>--- a/src/southbridge/via/vt8237r/pirq.c<br>+++ b/src/southbridge/via/vt8237r/pirq.c<br>@@ -21,7 +21,7 @@<br> #include <device/pci_ids.h><br> #include <pc80/i8259.h><br> <br>-#if (CONFIG_PIRQ_ROUTE == 1 && CONFIG_GENERATE_PIRQ_TABLE == 1)<br>+#if IS_ENABLED(CONFIG_PIRQ_ROUTE) && IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)<br> void pirq_assign_irqs(const unsigned char route[4])<br> {<br> device_t pdev;<br>diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c<br>index 42da53a..057a07d 100644<br>--- a/src/southbridge/via/vt8237r/usb.c<br>+++ b/src/southbridge/via/vt8237r/usb.c<br>@@ -21,13 +21,13 @@<br> #include "chip.h"<br> #include "vt8237r.h"<br> <br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800};<br> #endif<br> <br> static void usb_i_init(struct device *dev)<br> {<br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> u8 reg8;<br> <br> printk(BIOS_DEBUG, "Entering %s\n", __func__);<br>@@ -66,7 +66,7 @@<br> <br> static void vt8237_usb_i_read_resources(struct device *dev)<br> {<br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> struct resource *res;<br> u8 function = (u8) dev->path.pci.devfn & 0x7;<br> <br>@@ -92,7 +92,7 @@<br> static void usb_ii_init(struct device *dev)<br> {<br> struct southbridge_via_vt8237r_config *cfg;<br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> u8 reg8;<br> <br> printk(BIOS_DEBUG, "Entering %s\n", __func__);<br>@@ -136,7 +136,7 @@<br> <br> static void vt8237_usb_ii_read_resources(struct device *dev)<br> {<br>-#if CONFIG_EPIA_VT8237R_INIT<br>+#if IS_ENABLED(CONFIG_EPIA_VT8237R_INIT)<br> struct resource *res;<br> <br> /* Fix the I/O Resources of the USB2.0 Interface */<br>diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h<br>index 95f9750..f58b691 100644<br>--- a/src/southbridge/via/vt8237r/vt8237r.h<br>+++ b/src/southbridge/via/vt8237r/vt8237r.h<br>@@ -89,7 +89,7 @@<br> #define I2C_TRANS_CMD 0x40<br> #define CLOCK_SLAVE_ADDRESS 0x69<br> <br>-#if CONFIG_DEBUG_SMBUS<br>+#if IS_ENABLED(CONFIG_DEBUG_SMBUS)<br> #define PRINT_DEBUG(x) printk(BIOS_DEBUG, x)<br> #define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x)<br> #else<br></pre><p>To view, visit <a href="https://review.coreboot.org/20353">change 20353</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20353"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie965cbcf7f7b6f6c9e9a69e2a1ff0ba491246cbe </div>
<div style="display:none"> Gerrit-Change-Number: 20353 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>