[coreboot-gerrit] Change in coreboot[master]: southbridge/intel: add IS_ENABLED() around Kconfig symbol re...
Martin Roth (Code Review)
gerrit at coreboot.org
Sun Jun 25 21:07:14 CEST 2017
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20350
Change subject: southbridge/intel: add IS_ENABLED() around Kconfig symbol references
......................................................................
southbridge/intel: add IS_ENABLED() around Kconfig symbol references
Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/southbridge/intel/bd82x6x/finalize.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/smi.c
M src/southbridge/intel/bd82x6x/smihandler.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/common/usb_debug.c
M src/southbridge/intel/fsp_bd82x6x/early_init.c
M src/southbridge/intel/fsp_bd82x6x/finalize.c
M src/southbridge/intel/fsp_bd82x6x/lpc.c
M src/southbridge/intel/fsp_bd82x6x/me.c
M src/southbridge/intel/fsp_bd82x6x/me_8.x.c
M src/southbridge/intel/fsp_bd82x6x/pch.h
M src/southbridge/intel/fsp_bd82x6x/smi.c
M src/southbridge/intel/fsp_bd82x6x/smihandler.c
M src/southbridge/intel/fsp_i89xx/early_init.c
M src/southbridge/intel/fsp_i89xx/finalize.c
M src/southbridge/intel/fsp_i89xx/lpc.c
M src/southbridge/intel/fsp_i89xx/me.c
M src/southbridge/intel/fsp_i89xx/me_8.x.c
M src/southbridge/intel/fsp_i89xx/pch.h
M src/southbridge/intel/fsp_i89xx/romstage.c
M src/southbridge/intel/fsp_i89xx/smi.c
M src/southbridge/intel/fsp_i89xx/smihandler.c
M src/southbridge/intel/fsp_rangeley/lpc.c
M src/southbridge/intel/fsp_rangeley/soc.h
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/smihandler.c
M src/southbridge/intel/i82801ix/acpi/sleepstates.asl
M src/southbridge/intel/i82801ix/i82801ix.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/pch.h
M src/southbridge/intel/ibexpeak/smi.c
M src/southbridge/intel/ibexpeak/smihandler.c
M src/southbridge/intel/lynxpoint/acpi/pch.asl
M src/southbridge/intel/lynxpoint/early_pch.c
M src/southbridge/intel/lynxpoint/finalize.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/pmutil.c
M src/southbridge/intel/lynxpoint/smi.c
M src/southbridge/intel/lynxpoint/smihandler.c
48 files changed, 119 insertions(+), 119 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/20350/1
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index 9c453e4..a9cfa38 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -45,7 +45,7 @@
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
-#if CONFIG_SPI_FLASH_SMM
+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index c9fee89..bb9b817 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -76,7 +76,7 @@
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
-#if !CONFIG_SERIRQ_CONTINUOUS_MODE
+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@@ -285,7 +285,7 @@
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}
@@ -668,7 +668,7 @@
gnvs->ndid = gfx->ndid;
memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
chromeos_init_vboot(&(gnvs->chromeos));
#endif
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 0e5187c..70ba301 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -42,7 +42,7 @@
#include "me.h"
#include "pch.h"
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -61,7 +61,7 @@
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -457,7 +457,7 @@
}
#endif
-#if CONFIG_CHROMEOS && 0 /* DISABLED */
+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
int mkhi_global_reset(void)
{
@@ -589,7 +589,7 @@
if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -678,7 +678,7 @@
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 94cec3e..2e29233 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -42,7 +42,7 @@
#include "me.h"
#include "pch.h"
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -63,7 +63,7 @@
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -424,7 +424,7 @@
}
#endif
-#if CONFIG_CHROMEOS && 0 /* DISABLED */
+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
static int mkhi_global_reset(void)
{
@@ -576,7 +576,7 @@
path = ME_ERROR_BIOS_PATH;
}
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -665,7 +665,7 @@
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
@@ -706,7 +706,7 @@
if (intel_me_read_mbp(&mbp_data))
break;
-#if CONFIG_CHROMEOS && 0 /* DISABLED */
+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/*
* Unlock ME in recovery mode.
*/
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 1e05c9c..0ae9826 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -75,7 +75,7 @@
int pch_silicon_supported(int type, int rev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void gpi_route_interrupt(u8 gpi, u8 mode);
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
void pch_log_state(void);
#endif
#else /* __PRE_RAM__ */
diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c
index c7cb146..2248904 100644
--- a/src/southbridge/intel/bd82x6x/smi.c
+++ b/src/southbridge/intel/bd82x6x/smi.c
@@ -227,7 +227,7 @@
u16 pm1_en;
u32 gpe0_en;
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 4cef988..165acab 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -432,7 +432,7 @@
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -534,7 +534,7 @@
return NULL;
}
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -621,7 +621,7 @@
mainboard_finalized = 1;
break;
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@@ -645,7 +645,7 @@
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
outl(reg32, pmbase + PM1_CNT);
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 13db224..486d0db 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -187,7 +187,7 @@
SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
};
-#if CONFIG_DEBUG_SPI_FLASH
+#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
static u8 readb_(const void *addr)
{
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index 23c732f..eeac6d9 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -27,7 +27,7 @@
u32 class;
pci_devfn_t dev;
-#if CONFIG_HAVE_USBDEBUG_OPTIONS
+#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)
if (hcd_idx==2)
dev = PCI_DEV(0, 0x1a, 0);
else
@@ -37,7 +37,7 @@
#endif
class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
-#if CONFIG_HAVE_USBDEBUG_OPTIONS
+#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)
if (class != PCI_EHCI_CLASSCODE) {
/* If we enter here before RCBA programming, EHCI function may
* appear with the highest function number instead.
diff --git a/src/southbridge/intel/fsp_bd82x6x/early_init.c b/src/southbridge/intel/fsp_bd82x6x/early_init.c
index 54329c3..f9f3134 100644
--- a/src/southbridge/intel/fsp_bd82x6x/early_init.c
+++ b/src/southbridge/intel/fsp_bd82x6x/early_init.c
@@ -151,7 +151,7 @@
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
printk(BIOS_DEBUG, " done.\n");
-#if CONFIG_ELOG_BOOT_COUNT
+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter for non-S3 resume */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
@@ -160,7 +160,7 @@
printk(BIOS_DEBUG, " done.\n");
-#if CONFIG_ELOG_BOOT_COUNT
+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter except when resuming from S3 */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)
diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c
index 22165b9..5b65fb0 100644
--- a/src/southbridge/intel/fsp_bd82x6x/finalize.c
+++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c
@@ -30,7 +30,7 @@
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
-#if CONFIG_SPI_FLASH_SMM
+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index 963359f..4a5bf68 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -85,7 +85,7 @@
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
-#if !CONFIG_SERIRQ_CONTINUOUS_MODE
+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@@ -295,7 +295,7 @@
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index a634134..a4b5f03 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -41,7 +41,7 @@
#include "me.h"
#include "pch.h"
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -60,7 +60,7 @@
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -456,7 +456,7 @@
}
#endif
-#if CONFIG_CHROMEOS && 0 /* DISABLED */
+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
int mkhi_global_reset(void)
{
@@ -588,7 +588,7 @@
if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -677,7 +677,7 @@
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index 4001fb9..d89502e 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -40,7 +40,7 @@
#include "me.h"
#include "pch.h"
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -61,7 +61,7 @@
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -422,7 +422,7 @@
}
#endif
-#if CONFIG_CHROMEOS && 0 /* DISABLED */
+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
static int mkhi_global_reset(void)
{
@@ -574,7 +574,7 @@
path = ME_ERROR_BIOS_PATH;
}
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -663,7 +663,7 @@
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
@@ -704,7 +704,7 @@
if (intel_me_read_mbp(&mbp_data))
break;
-#if CONFIG_CHROMEOS && 0 /* DISABLED */
+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/*
* Unlock ME in recovery mode.
*/
diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h
index 7fe40f7..84f21a7 100644
--- a/src/southbridge/intel/fsp_bd82x6x/pch.h
+++ b/src/southbridge/intel/fsp_bd82x6x/pch.h
@@ -67,7 +67,7 @@
int pch_silicon_supported(int type, int rev);
void pch_enable(device_t dev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
void pch_log_state(void);
#endif
#else
diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c
index d97801e..14637e6 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smi.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smi.c
@@ -227,7 +227,7 @@
u16 pm1_en;
u32 gpe0_en;
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif
diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
index 19337e9..394e0a9 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
@@ -331,7 +331,7 @@
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -433,7 +433,7 @@
return NULL;
}
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -505,7 +505,7 @@
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@@ -529,7 +529,7 @@
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
outl(reg32, pmbase + PM1_CNT);
diff --git a/src/southbridge/intel/fsp_i89xx/early_init.c b/src/southbridge/intel/fsp_i89xx/early_init.c
index 887bf3c..7ce3c7f 100644
--- a/src/southbridge/intel/fsp_i89xx/early_init.c
+++ b/src/southbridge/intel/fsp_i89xx/early_init.c
@@ -38,7 +38,7 @@
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
printk(BIOS_DEBUG, " done.\n");
-#if CONFIG_ELOG_BOOT_COUNT
+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter for non-S3 resume */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
@@ -47,7 +47,7 @@
printk(BIOS_DEBUG, " done.\n");
-#if CONFIG_ELOG_BOOT_COUNT
+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter except when resuming from S3 */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)
diff --git a/src/southbridge/intel/fsp_i89xx/finalize.c b/src/southbridge/intel/fsp_i89xx/finalize.c
index 22165b9..5b65fb0 100644
--- a/src/southbridge/intel/fsp_i89xx/finalize.c
+++ b/src/southbridge/intel/fsp_i89xx/finalize.c
@@ -30,7 +30,7 @@
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
-#if CONFIG_SPI_FLASH_SMM
+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif
diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c
index 5ba2969..8a815c5 100644
--- a/src/southbridge/intel/fsp_i89xx/lpc.c
+++ b/src/southbridge/intel/fsp_i89xx/lpc.c
@@ -85,7 +85,7 @@
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
-#if !CONFIG_SERIRQ_CONTINUOUS_MODE
+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@@ -295,7 +295,7 @@
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}
diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c
index 704f209..4b5a4b3 100644
--- a/src/southbridge/intel/fsp_i89xx/me.c
+++ b/src/southbridge/intel/fsp_i89xx/me.c
@@ -41,7 +41,7 @@
#include "me.h"
#include "pch.h"
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -60,7 +60,7 @@
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -555,7 +555,7 @@
if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -644,7 +644,7 @@
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c
index b68a5dc..b094524 100644
--- a/src/southbridge/intel/fsp_i89xx/me_8.x.c
+++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c
@@ -40,7 +40,7 @@
#include "me.h"
#include "pch.h"
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -61,7 +61,7 @@
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -543,7 +543,7 @@
path = ME_ERROR_BIOS_PATH;
}
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -632,7 +632,7 @@
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h
index 6d8b873..9ae9467 100644
--- a/src/southbridge/intel/fsp_i89xx/pch.h
+++ b/src/southbridge/intel/fsp_i89xx/pch.h
@@ -65,7 +65,7 @@
int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_enable(device_t dev);
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
void pch_log_state(void);
#endif
#else
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c
index c2b5221..385e4d6 100644
--- a/src/southbridge/intel/fsp_i89xx/romstage.c
+++ b/src/southbridge/intel/fsp_i89xx/romstage.c
@@ -137,7 +137,7 @@
pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
post_code(0x46);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but
diff --git a/src/southbridge/intel/fsp_i89xx/smi.c b/src/southbridge/intel/fsp_i89xx/smi.c
index f28d966..6dc58f0 100644
--- a/src/southbridge/intel/fsp_i89xx/smi.c
+++ b/src/southbridge/intel/fsp_i89xx/smi.c
@@ -227,7 +227,7 @@
u16 pm1_en;
u32 gpe0_en;
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif
diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c
index 099fb84..ff76c20 100644
--- a/src/southbridge/intel/fsp_i89xx/smihandler.c
+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c
@@ -331,7 +331,7 @@
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -433,7 +433,7 @@
return NULL;
}
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -505,7 +505,7 @@
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@@ -529,7 +529,7 @@
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
outl(reg32, pmbase + PM1_CNT);
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index d621a41..cbb2297 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -94,7 +94,7 @@
/* Set packet length and toggle silent mode bit for one frame. */
write8(ibase + ILB_SERIRQ_CNTL, (1 << 7));
-#if !CONFIG_SERIRQ_CONTINUOUS_MODE
+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
write8(ibase + ILB_SERIRQ_CNTL, 0);
#endif
}
@@ -435,7 +435,7 @@
memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs);
acpi_save_gnvs((unsigned long)gnvs);
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
#endif
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index 0674dca..4409f1e 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -65,7 +65,7 @@
#include <arch/acpi.h>
void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt);
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
void soc_log_state(void);
#endif
#else
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index bd0e964..2bab05c 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -28,7 +28,7 @@
#endif
#include "i82371eb.h"
-#if CONFIG_IOAPIC
+#if IS_ENABLED(CONFIG_IOAPIC)
static void enable_intel_82093aa_ioapic(void)
{
u16 reg16;
@@ -84,7 +84,7 @@
/* Initialize ISA DMA. */
isa_dma_init();
-#if CONFIG_IOAPIC
+#if IS_ENABLED(CONFIG_IOAPIC)
/*
* Unlike most other southbridges the 82371EB doesn't have a built-in
* IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
@@ -115,7 +115,7 @@
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
IORESOURCE_RESERVE;
-#if CONFIG_IOAPIC
+#if IS_ENABLED(CONFIG_IOAPIC)
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index e650d82..a26b9f8 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -329,7 +329,7 @@
RCBA32(CG) = reg32;
}
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
static void i82801gx_lock_smm(struct device *dev)
{
#if TEST_SMM_FLASH_LOCKDOWN
@@ -448,7 +448,7 @@
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
i82801gx_lock_smm(dev);
#endif
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 6bd9517..d3c32fd 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -414,7 +414,7 @@
printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
}
-#if !CONFIG_SMM_TSEG
+#if !IS_ENABLED(CONFIG_SMM_TSEG)
/* Unlock the SMI semaphore. We're currently in SMM, and the semaphore
* will never be unlocked because the next outl will switch off the CPU.
* This might open a small race between the smi_release_lock() and the outl()
diff --git a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl
index 62bb026..d7fb2a5 100644
--- a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl
+++ b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl
@@ -15,7 +15,7 @@
*/
Name(\_S0, Package(){0x0,0x0,0x0,0x0})
-#if !CONFIG_HAVE_ACPI_RESUME
+#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
Name(\_S1, Package(){0x1,0x0,0x0,0x0})
#else
Name(\_S3, Package(){0x5,0x0,0x0,0x0})
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index 0f3a08c..7d44fba 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -222,7 +222,7 @@
i82801ix_hide_functions();
/* Reset watchdog timer. */
-#if !CONFIG_HAVE_SMI_HANDLER
+#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */
#endif
outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 8212b0a..bc45b9d 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -369,7 +369,7 @@
RCBA32(0x38c0) |= 7;
}
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
static void i82801ix_lock_smm(struct device *dev)
{
#if TEST_SMM_FLASH_LOCKDOWN
@@ -464,7 +464,7 @@
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
i82801ix_lock_smm(dev);
#endif
}
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index f01d8b2..a152dfe 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -71,7 +71,7 @@
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
-#if !CONFIG_SERIRQ_CONTINUOUS_MODE
+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@@ -280,7 +280,7 @@
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index da6bfa8..70dbcbf 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -41,7 +41,7 @@
#include "me.h"
#include "pch.h"
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -60,7 +60,7 @@
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -470,7 +470,7 @@
if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -559,7 +559,7 @@
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index d87f8e0..63307d9 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -70,7 +70,7 @@
int pch_silicon_supported(int type, int rev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void gpi_route_interrupt(u8 gpi, u8 mode);
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
void pch_log_state(void);
#endif
#else /* __PRE_RAM__ */
diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c
index 950dbe0..f1bcf03 100644
--- a/src/southbridge/intel/ibexpeak/smi.c
+++ b/src/southbridge/intel/ibexpeak/smi.c
@@ -228,7 +228,7 @@
u16 pm1_en;
u32 gpe0_en;
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index a0b963e..88f64f1 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -433,7 +433,7 @@
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -535,7 +535,7 @@
return NULL;
}
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -607,7 +607,7 @@
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@@ -631,7 +631,7 @@
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
outl(reg32, pmbase + PM1_CNT);
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl
index c30bfa4..fbbd26d 100644
--- a/src/southbridge/intel/lynxpoint/acpi/pch.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl
@@ -96,7 +96,7 @@
#include "smbus.asl"
// Serial IO
-#if CONFIG_INTEL_LYNXPOINT_LP
+#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
#include "serialio.asl"
#include "lpt_lp.asl"
#endif
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 0e4fa3d..cb4bc7e 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -24,7 +24,7 @@
#include "pch.h"
#include "chip.h"
-#if CONFIG_INTEL_LYNXPOINT_LP
+#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
#include "lp_gpio.h"
#else
#include "southbridge/intel/common/gpio.h"
@@ -133,7 +133,7 @@
pch_enable_bars();
-#if CONFIG_INTEL_LYNXPOINT_LP
+#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
setup_pch_lp_gpios(gpio_map);
#else
setup_pch_gpios(gpio_map);
@@ -154,7 +154,7 @@
wake_from_s3 = sleep_type_s3();
-#if CONFIG_ELOG_BOOT_COUNT
+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
if (!wake_from_s3)
boot_count_increment();
#endif
diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c
index 1ff38e9..39a555e 100644
--- a/src/southbridge/intel/lynxpoint/finalize.c
+++ b/src/southbridge/intel/lynxpoint/finalize.c
@@ -34,7 +34,7 @@
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
-#if CONFIG_SPI_FLASH_SMM
+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index d295c88..55edaf9 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -77,7 +77,7 @@
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
-#if !CONFIG_SERIRQ_CONTINUOUS_MODE
+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@@ -292,7 +292,7 @@
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}
@@ -498,7 +498,7 @@
static void pch_set_acpi_mode(void)
{
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
@@ -760,7 +760,7 @@
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
chromeos_init_vboot(&(gnvs->chromeos));
#endif
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 355db4b..c393feb 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -37,7 +37,7 @@
#include "me.h"
#include "pch.h"
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -59,7 +59,7 @@
static u32 *mei_base_address;
void intel_me_mbp_clear(device_t dev);
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -519,7 +519,7 @@
#endif /* CONFIG_DEBUG_INTEL_ME */
#endif
-#if CONFIG_CHROMEOS && 0 /* DISABLED */
+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
static int mkhi_global_reset(void)
{
@@ -579,7 +579,7 @@
if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
-#if CONFIG_ME_MBP_CLEAR_LATE
+#if IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE)
/* Wait for ME MBP Cleared indicator */
intel_me_mbp_clear(PCH_ME_DEV);
#endif
@@ -707,7 +707,7 @@
path = ME_ERROR_BIOS_PATH;
}
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -796,7 +796,7 @@
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
@@ -835,7 +835,7 @@
#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
me_print_fw_version(mbp_data.fw_version_name);
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
me_print_fwcaps(mbp_data.fw_capabilities);
#endif
@@ -991,7 +991,7 @@
host.interrupt_generate = 1;
write_host_csr(&host);
-#if !CONFIG_ME_MBP_CLEAR_LATE
+#if !IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE)
/* Wait for the mbp_cleared indicator. */
intel_me_mbp_clear(dev);
#endif
@@ -1000,7 +1000,7 @@
#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",
mbp->header.num_entries, mbp->header.mbp_size);
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
for (i = 0; i < mbp->header.mbp_size - 1; i++) {
printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]);
}
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 8cae50a..9b061c6 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -72,7 +72,7 @@
#define SMBUS_IO_BASE 0x0400
#define SMBUS_SLAVE_ADDR 0x24
-#if CONFIG_INTEL_LYNXPOINT_LP
+#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
#define DEFAULT_PMBASE 0x1000
#define DEFAULT_GPIOBASE 0x1400
#define DEFAULT_GPIOSIZE 0x400
@@ -181,7 +181,7 @@
u32 pch_iobp_read(u32 address);
void pch_iobp_write(u32 address, u32 data);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
void pch_log_state(void);
#endif
void acpi_create_intel_hpet(acpi_hpet_t * hpet);
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index 90045d1..d70cb5d 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -26,7 +26,7 @@
#include <console/console.h>
#include "pch.h"
-#if CONFIG_INTEL_LYNXPOINT_LP
+#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
#include "lp_gpio.h"
#endif
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index 8c9cb58..5f1bdf7 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -29,7 +29,7 @@
{
u32 smi_en;
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif
@@ -123,7 +123,7 @@
/*
* Finalize system before payload boot if not in ChromeOS environment.
*/
-#if !CONFIG_CHROMEOS
+#if !IS_ENABLED(CONFIG_CHROMEOS)
static void finalize_boot(void *unused)
{
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 0102308..37a7a2b 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -130,13 +130,13 @@
mainboard_smi_sleep(slp_typ);
/* USB sleep preparations */
-#if !CONFIG_FINALIZE_USB_ROUTE_XHCI
+#if !IS_ENABLED(CONFIG_FINALIZE_USB_ROUTE_XHCI)
usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ);
usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ);
#endif
usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ);
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -243,7 +243,7 @@
return NULL;
}
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -314,7 +314,7 @@
case 0xca:
usb_xhci_route_all();
break;
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@@ -333,7 +333,7 @@
*/
if (pm1_sts & PWRBTN_STS) {
// power button pressed
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
disable_pm1_control(-1UL);
--
To view, visit https://review.coreboot.org/20350
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45
Gerrit-Change-Number: 20350
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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