<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20350">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">southbridge/intel: add IS_ENABLED() around Kconfig symbol references<br><br>Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/southbridge/intel/bd82x6x/finalize.c<br>M src/southbridge/intel/bd82x6x/lpc.c<br>M src/southbridge/intel/bd82x6x/me.c<br>M src/southbridge/intel/bd82x6x/me_8.x.c<br>M src/southbridge/intel/bd82x6x/pch.h<br>M src/southbridge/intel/bd82x6x/smi.c<br>M src/southbridge/intel/bd82x6x/smihandler.c<br>M src/southbridge/intel/common/spi.c<br>M src/southbridge/intel/common/usb_debug.c<br>M src/southbridge/intel/fsp_bd82x6x/early_init.c<br>M src/southbridge/intel/fsp_bd82x6x/finalize.c<br>M src/southbridge/intel/fsp_bd82x6x/lpc.c<br>M src/southbridge/intel/fsp_bd82x6x/me.c<br>M src/southbridge/intel/fsp_bd82x6x/me_8.x.c<br>M src/southbridge/intel/fsp_bd82x6x/pch.h<br>M src/southbridge/intel/fsp_bd82x6x/smi.c<br>M src/southbridge/intel/fsp_bd82x6x/smihandler.c<br>M src/southbridge/intel/fsp_i89xx/early_init.c<br>M src/southbridge/intel/fsp_i89xx/finalize.c<br>M src/southbridge/intel/fsp_i89xx/lpc.c<br>M src/southbridge/intel/fsp_i89xx/me.c<br>M src/southbridge/intel/fsp_i89xx/me_8.x.c<br>M src/southbridge/intel/fsp_i89xx/pch.h<br>M src/southbridge/intel/fsp_i89xx/romstage.c<br>M src/southbridge/intel/fsp_i89xx/smi.c<br>M src/southbridge/intel/fsp_i89xx/smihandler.c<br>M src/southbridge/intel/fsp_rangeley/lpc.c<br>M src/southbridge/intel/fsp_rangeley/soc.h<br>M src/southbridge/intel/i82371eb/isa.c<br>M src/southbridge/intel/i82801gx/lpc.c<br>M src/southbridge/intel/i82801gx/smihandler.c<br>M src/southbridge/intel/i82801ix/acpi/sleepstates.asl<br>M src/southbridge/intel/i82801ix/i82801ix.c<br>M src/southbridge/intel/i82801ix/lpc.c<br>M src/southbridge/intel/ibexpeak/lpc.c<br>M src/southbridge/intel/ibexpeak/me.c<br>M src/southbridge/intel/ibexpeak/pch.h<br>M src/southbridge/intel/ibexpeak/smi.c<br>M src/southbridge/intel/ibexpeak/smihandler.c<br>M src/southbridge/intel/lynxpoint/acpi/pch.asl<br>M src/southbridge/intel/lynxpoint/early_pch.c<br>M src/southbridge/intel/lynxpoint/finalize.c<br>M src/southbridge/intel/lynxpoint/lpc.c<br>M src/southbridge/intel/lynxpoint/me_9.x.c<br>M src/southbridge/intel/lynxpoint/pch.h<br>M src/southbridge/intel/lynxpoint/pmutil.c<br>M src/southbridge/intel/lynxpoint/smi.c<br>M src/southbridge/intel/lynxpoint/smihandler.c<br>48 files changed, 119 insertions(+), 119 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/20350/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c<br>index 9c453e4..a9cfa38 100644<br>--- a/src/southbridge/intel/bd82x6x/finalize.c<br>+++ b/src/southbridge/intel/bd82x6x/finalize.c<br>@@ -45,7 +45,7 @@<br>     /* Lock SPIBAR */<br>     RCBA32_OR(0x3804, (1 << 15));<br> <br>-#if CONFIG_SPI_FLASH_SMM<br>+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)<br>      /* Re-init SPI driver to handle locked BAR */<br>         spi_init();<br> #endif<br>diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c<br>index c9fee89..bb9b817 100644<br>--- a/src/southbridge/intel/bd82x6x/lpc.c<br>+++ b/src/southbridge/intel/bd82x6x/lpc.c<br>@@ -76,7 +76,7 @@<br>  /* Set packet length and toggle silent mode bit for one frame. */<br>     pci_write_config8(dev, SERIRQ_CNTL,<br>                     (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));<br>-#if !CONFIG_SERIRQ_CONTINUOUS_MODE<br>+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)<br>   pci_write_config8(dev, SERIRQ_CNTL,<br>                     (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));<br> #endif<br>@@ -285,7 +285,7 @@<br>   if (rtc_failed) {<br>             reg8 &= ~RTC_BATTERY_DEAD;<br>                pci_write_config8(dev, GEN_PMCON_3, reg8);<br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>            elog_add_event(ELOG_TYPE_RTC_RESET);<br> #endif<br>         }<br>@@ -668,7 +668,7 @@<br>                gnvs->ndid = gfx->ndid;<br>                 memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br>           chromeos_init_vboot(&(gnvs->chromeos));<br> #endif<br> <br>diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c<br>index 0e5187c..70ba301 100644<br>--- a/src/southbridge/intel/bd82x6x/me.c<br>+++ b/src/southbridge/intel/bd82x6x/me.c<br>@@ -42,7 +42,7 @@<br> #include "me.h"<br> #include "pch.h"<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> #include <vendorcode/google/chromeos/gnvs.h><br> #endif<br> <br>@@ -61,7 +61,7 @@<br> /* MMIO base address for MEI interface */<br> static u32 *mei_base_address;<br> <br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br> static void mei_dump(void *ptr, int dword, int offset, const char *type)<br> {<br>      struct mei_csr *csr;<br>@@ -457,7 +457,7 @@<br> }<br> #endif<br> <br>-#if CONFIG_CHROMEOS && 0 /* DISABLED */<br>+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */<br> /* Tell ME to issue a global reset */<br> int mkhi_global_reset(void)<br> {<br>@@ -589,7 +589,7 @@<br>      if (hfs.error_code || hfs.fpt_bad)<br>            path = ME_ERROR_BIOS_PATH;<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>         if (path != ME_NORMAL_BIOS_PATH) {<br>            struct elog_event_data_me_extended data = {<br>                   .current_working_state = hfs.working_state,<br>@@ -678,7 +678,7 @@<br>      }<br>     printk(BIOS_DEBUG, "\n");<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br>        /* Save hash in NVS for the OS to verify */<br>   chromeos_set_me_hash(extend, count);<br> #endif<br>diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c<br>index 94cec3e..2e29233 100644<br>--- a/src/southbridge/intel/bd82x6x/me_8.x.c<br>+++ b/src/southbridge/intel/bd82x6x/me_8.x.c<br>@@ -42,7 +42,7 @@<br> #include "me.h"<br> #include "pch.h"<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> #include <vendorcode/google/chromeos/chromeos.h><br> #include <vendorcode/google/chromeos/gnvs.h><br> #endif<br>@@ -63,7 +63,7 @@<br> /* MMIO base address for MEI interface */<br> static u32 *mei_base_address;<br> <br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br> static void mei_dump(void *ptr, int dword, int offset, const char *type)<br> {<br>     struct mei_csr *csr;<br>@@ -424,7 +424,7 @@<br> }<br> #endif<br> <br>-#if CONFIG_CHROMEOS && 0 /* DISABLED */<br>+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */<br> /* Tell ME to issue a global reset */<br> static int mkhi_global_reset(void)<br> {<br>@@ -576,7 +576,7 @@<br>               path = ME_ERROR_BIOS_PATH;<br>    }<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>  if (path != ME_NORMAL_BIOS_PATH) {<br>            struct elog_event_data_me_extended data = {<br>                   .current_working_state = hfs.working_state,<br>@@ -665,7 +665,7 @@<br>      }<br>     printk(BIOS_DEBUG, "\n");<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br>        /* Save hash in NVS for the OS to verify */<br>   chromeos_set_me_hash(extend, count);<br> #endif<br>@@ -706,7 +706,7 @@<br>            if (intel_me_read_mbp(&mbp_data))<br>                         break;<br> <br>-#if CONFIG_CHROMEOS && 0 /* DISABLED */<br>+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */<br>             /*<br>             * Unlock ME in recovery mode.<br>                 */<br>diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h<br>index 1e05c9c..0ae9826 100644<br>--- a/src/southbridge/intel/bd82x6x/pch.h<br>+++ b/src/southbridge/intel/bd82x6x/pch.h<br>@@ -75,7 +75,7 @@<br> int pch_silicon_supported(int type, int rev);<br> void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);<br> void gpi_route_interrupt(u8 gpi, u8 mode);<br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br> void pch_log_state(void);<br> #endif<br> #else /* __PRE_RAM__ */<br>diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c<br>index c7cb146..2248904 100644<br>--- a/src/southbridge/intel/bd82x6x/smi.c<br>+++ b/src/southbridge/intel/bd82x6x/smi.c<br>@@ -227,7 +227,7 @@<br>     u16 pm1_en;<br>   u32 gpe0_en;<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>       /* Log events from chipset before clearing */<br>         pch_log_state();<br> #endif<br>diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c<br>index 4cef988..165acab 100644<br>--- a/src/southbridge/intel/bd82x6x/smihandler.c<br>+++ b/src/southbridge/intel/bd82x6x/smihandler.c<br>@@ -432,7 +432,7 @@<br>       /* Do any mainboard sleep handling */<br>         mainboard_smi_sleep(slp_typ);<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>    /* Log S3, S4, and S5 entry */<br>        if (slp_typ >= ACPI_S3)<br>            elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);<br>@@ -534,7 +534,7 @@<br>      return NULL;<br> }<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> static void southbridge_smi_gsmi(void)<br> {<br>    u32 *ret, *param;<br>@@ -621,7 +621,7 @@<br> <br>             mainboard_finalized = 1;<br>              break;<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>      case ELOG_GSMI_APM_CNT:<br>               southbridge_smi_gsmi();<br>               break;<br>@@ -645,7 +645,7 @@<br>           // power button pressed<br>               u32 reg32;<br>            reg32 = (7 << 10) | (1 << 13);<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>          elog_add_event(ELOG_TYPE_POWER_BUTTON);<br> #endif<br>              outl(reg32, pmbase + PM1_CNT);<br>diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c<br>index 13db224..486d0db 100644<br>--- a/src/southbridge/intel/common/spi.c<br>+++ b/src/southbridge/intel/common/spi.c<br>@@ -187,7 +187,7 @@<br>  SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS =    3<br> };<br> <br>-#if CONFIG_DEBUG_SPI_FLASH<br>+#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)<br> <br> static u8 readb_(const void *addr)<br> {<br>diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c<br>index 23c732f..eeac6d9 100644<br>--- a/src/southbridge/intel/common/usb_debug.c<br>+++ b/src/southbridge/intel/common/usb_debug.c<br>@@ -27,7 +27,7 @@<br>       u32 class;<br>    pci_devfn_t dev;<br> <br>-#if CONFIG_HAVE_USBDEBUG_OPTIONS<br>+#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)<br>         if (hcd_idx==2)<br>               dev = PCI_DEV(0, 0x1a, 0);<br>    else<br>@@ -37,7 +37,7 @@<br> #endif<br> <br>   class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;<br>-#if CONFIG_HAVE_USBDEBUG_OPTIONS<br>+#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)<br>      if (class != PCI_EHCI_CLASSCODE) {<br>            /* If we enter here before RCBA programming, EHCI function may<br>                 * appear with the highest function number instead.<br>diff --git a/src/southbridge/intel/fsp_bd82x6x/early_init.c b/src/southbridge/intel/fsp_bd82x6x/early_init.c<br>index 54329c3..f9f3134 100644<br>--- a/src/southbridge/intel/fsp_bd82x6x/early_init.c<br>+++ b/src/southbridge/intel/fsp_bd82x6x/early_init.c<br>@@ -151,7 +151,7 @@<br>     outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);    /* halt timer */<br>      printk(BIOS_DEBUG, " done.\n");<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br>    /* Increment Boot Counter for non-S3 resume */<br>        if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&<br>      ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)<br>@@ -160,7 +160,7 @@<br> <br>      printk(BIOS_DEBUG, " done.\n");<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br>    /* Increment Boot Counter except when resuming from S3 */<br>     if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&<br>      ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)<br>diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c<br>index 22165b9..5b65fb0 100644<br>--- a/src/southbridge/intel/fsp_bd82x6x/finalize.c<br>+++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c<br>@@ -30,7 +30,7 @@<br>  /* Lock SPIBAR */<br>     RCBA32_OR(0x3804, (1 << 15));<br> <br>-#if CONFIG_SPI_FLASH_SMM<br>+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)<br>      /* Re-init SPI driver to handle locked BAR */<br>         spi_init();<br> #endif<br>diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c<br>index 963359f..4a5bf68 100644<br>--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c<br>+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c<br>@@ -85,7 +85,7 @@<br>  /* Set packet length and toggle silent mode bit for one frame. */<br>     pci_write_config8(dev, SERIRQ_CNTL,<br>                     (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));<br>-#if !CONFIG_SERIRQ_CONTINUOUS_MODE<br>+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)<br>   pci_write_config8(dev, SERIRQ_CNTL,<br>                     (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));<br> #endif<br>@@ -295,7 +295,7 @@<br>   if (rtc_failed) {<br>             reg8 &= ~RTC_BATTERY_DEAD;<br>                pci_write_config8(dev, GEN_PMCON_3, reg8);<br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>            elog_add_event(ELOG_TYPE_RTC_RESET);<br> #endif<br>         }<br>diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c<br>index a634134..a4b5f03 100644<br>--- a/src/southbridge/intel/fsp_bd82x6x/me.c<br>+++ b/src/southbridge/intel/fsp_bd82x6x/me.c<br>@@ -41,7 +41,7 @@<br> #include "me.h"<br> #include "pch.h"<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> #include <vendorcode/google/chromeos/gnvs.h><br> #endif<br> <br>@@ -60,7 +60,7 @@<br> /* MMIO base address for MEI interface */<br> static u32 *mei_base_address;<br> <br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br> static void mei_dump(void *ptr, int dword, int offset, const char *type)<br> {<br>       struct mei_csr *csr;<br>@@ -456,7 +456,7 @@<br> }<br> #endif<br> <br>-#if CONFIG_CHROMEOS && 0 /* DISABLED */<br>+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */<br> /* Tell ME to issue a global reset */<br> int mkhi_global_reset(void)<br> {<br>@@ -588,7 +588,7 @@<br>      if (hfs.error_code || hfs.fpt_bad)<br>            path = ME_ERROR_BIOS_PATH;<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>         if (path != ME_NORMAL_BIOS_PATH) {<br>            struct elog_event_data_me_extended data = {<br>                   .current_working_state = hfs.working_state,<br>@@ -677,7 +677,7 @@<br>      }<br>     printk(BIOS_DEBUG, "\n");<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br>        /* Save hash in NVS for the OS to verify */<br>   chromeos_set_me_hash(extend, count);<br> #endif<br>diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c<br>index 4001fb9..d89502e 100644<br>--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c<br>+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c<br>@@ -40,7 +40,7 @@<br> #include "me.h"<br> #include "pch.h"<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> #include <vendorcode/google/chromeos/chromeos.h><br> #include <vendorcode/google/chromeos/gnvs.h><br> #endif<br>@@ -61,7 +61,7 @@<br> /* MMIO base address for MEI interface */<br> static u32 *mei_base_address;<br> <br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br> static void mei_dump(void *ptr, int dword, int offset, const char *type)<br> {<br>     struct mei_csr *csr;<br>@@ -422,7 +422,7 @@<br> }<br> #endif<br> <br>-#if CONFIG_CHROMEOS && 0 /* DISABLED */<br>+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */<br> /* Tell ME to issue a global reset */<br> static int mkhi_global_reset(void)<br> {<br>@@ -574,7 +574,7 @@<br>               path = ME_ERROR_BIOS_PATH;<br>    }<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>  if (path != ME_NORMAL_BIOS_PATH) {<br>            struct elog_event_data_me_extended data = {<br>                   .current_working_state = hfs.working_state,<br>@@ -663,7 +663,7 @@<br>      }<br>     printk(BIOS_DEBUG, "\n");<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br>        /* Save hash in NVS for the OS to verify */<br>   chromeos_set_me_hash(extend, count);<br> #endif<br>@@ -704,7 +704,7 @@<br>            if (intel_me_read_mbp(&mbp_data))<br>                         break;<br> <br>-#if CONFIG_CHROMEOS && 0 /* DISABLED */<br>+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */<br>             /*<br>             * Unlock ME in recovery mode.<br>                 */<br>diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h<br>index 7fe40f7..84f21a7 100644<br>--- a/src/southbridge/intel/fsp_bd82x6x/pch.h<br>+++ b/src/southbridge/intel/fsp_bd82x6x/pch.h<br>@@ -67,7 +67,7 @@<br> int pch_silicon_supported(int type, int rev);<br> void pch_enable(device_t dev);<br> void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);<br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br> void pch_log_state(void);<br> #endif<br> #else<br>diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c<br>index d97801e..14637e6 100644<br>--- a/src/southbridge/intel/fsp_bd82x6x/smi.c<br>+++ b/src/southbridge/intel/fsp_bd82x6x/smi.c<br>@@ -227,7 +227,7 @@<br>   u16 pm1_en;<br>   u32 gpe0_en;<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>       /* Log events from chipset before clearing */<br>         pch_log_state();<br> #endif<br>diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c<br>index 19337e9..394e0a9 100644<br>--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c<br>+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c<br>@@ -331,7 +331,7 @@<br>       /* Do any mainboard sleep handling */<br>         mainboard_smi_sleep(slp_typ);<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>    /* Log S3, S4, and S5 entry */<br>        if (slp_typ >= ACPI_S3)<br>            elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);<br>@@ -433,7 +433,7 @@<br>      return NULL;<br> }<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> static void southbridge_smi_gsmi(void)<br> {<br>    u32 *ret, *param;<br>@@ -505,7 +505,7 @@<br>                        printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);<br>             }<br>             break;<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>      case ELOG_GSMI_APM_CNT:<br>               southbridge_smi_gsmi();<br>               break;<br>@@ -529,7 +529,7 @@<br>           // power button pressed<br>               u32 reg32;<br>            reg32 = (7 << 10) | (1 << 13);<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>          elog_add_event(ELOG_TYPE_POWER_BUTTON);<br> #endif<br>              outl(reg32, pmbase + PM1_CNT);<br>diff --git a/src/southbridge/intel/fsp_i89xx/early_init.c b/src/southbridge/intel/fsp_i89xx/early_init.c<br>index 887bf3c..7ce3c7f 100644<br>--- a/src/southbridge/intel/fsp_i89xx/early_init.c<br>+++ b/src/southbridge/intel/fsp_i89xx/early_init.c<br>@@ -38,7 +38,7 @@<br>    outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);    /* halt timer */<br>      printk(BIOS_DEBUG, " done.\n");<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br>    /* Increment Boot Counter for non-S3 resume */<br>        if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&<br>      ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)<br>@@ -47,7 +47,7 @@<br> <br>        printk(BIOS_DEBUG, " done.\n");<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br>    /* Increment Boot Counter except when resuming from S3 */<br>     if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&<br>      ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)<br>diff --git a/src/southbridge/intel/fsp_i89xx/finalize.c b/src/southbridge/intel/fsp_i89xx/finalize.c<br>index 22165b9..5b65fb0 100644<br>--- a/src/southbridge/intel/fsp_i89xx/finalize.c<br>+++ b/src/southbridge/intel/fsp_i89xx/finalize.c<br>@@ -30,7 +30,7 @@<br>  /* Lock SPIBAR */<br>     RCBA32_OR(0x3804, (1 << 15));<br> <br>-#if CONFIG_SPI_FLASH_SMM<br>+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)<br>      /* Re-init SPI driver to handle locked BAR */<br>         spi_init();<br> #endif<br>diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c<br>index 5ba2969..8a815c5 100644<br>--- a/src/southbridge/intel/fsp_i89xx/lpc.c<br>+++ b/src/southbridge/intel/fsp_i89xx/lpc.c<br>@@ -85,7 +85,7 @@<br>  /* Set packet length and toggle silent mode bit for one frame. */<br>     pci_write_config8(dev, SERIRQ_CNTL,<br>                     (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));<br>-#if !CONFIG_SERIRQ_CONTINUOUS_MODE<br>+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)<br>   pci_write_config8(dev, SERIRQ_CNTL,<br>                     (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));<br> #endif<br>@@ -295,7 +295,7 @@<br>   if (rtc_failed) {<br>             reg8 &= ~RTC_BATTERY_DEAD;<br>                pci_write_config8(dev, GEN_PMCON_3, reg8);<br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>            elog_add_event(ELOG_TYPE_RTC_RESET);<br> #endif<br>         }<br>diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c<br>index 704f209..4b5a4b3 100644<br>--- a/src/southbridge/intel/fsp_i89xx/me.c<br>+++ b/src/southbridge/intel/fsp_i89xx/me.c<br>@@ -41,7 +41,7 @@<br> #include "me.h"<br> #include "pch.h"<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> #include <vendorcode/google/chromeos/gnvs.h><br> #endif<br> <br>@@ -60,7 +60,7 @@<br> /* MMIO base address for MEI interface */<br> static u32 *mei_base_address;<br> <br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br> static void mei_dump(void *ptr, int dword, int offset, const char *type)<br> {<br>       struct mei_csr *csr;<br>@@ -555,7 +555,7 @@<br>     if (hfs.error_code || hfs.fpt_bad)<br>            path = ME_ERROR_BIOS_PATH;<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>         if (path != ME_NORMAL_BIOS_PATH) {<br>            struct elog_event_data_me_extended data = {<br>                   .current_working_state = hfs.working_state,<br>@@ -644,7 +644,7 @@<br>      }<br>     printk(BIOS_DEBUG, "\n");<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br>        /* Save hash in NVS for the OS to verify */<br>   chromeos_set_me_hash(extend, count);<br> #endif<br>diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c<br>index b68a5dc..b094524 100644<br>--- a/src/southbridge/intel/fsp_i89xx/me_8.x.c<br>+++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c<br>@@ -40,7 +40,7 @@<br> #include "me.h"<br> #include "pch.h"<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> #include <vendorcode/google/chromeos/chromeos.h><br> #include <vendorcode/google/chromeos/gnvs.h><br> #endif<br>@@ -61,7 +61,7 @@<br> /* MMIO base address for MEI interface */<br> static u32 *mei_base_address;<br> <br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br> static void mei_dump(void *ptr, int dword, int offset, const char *type)<br> {<br>     struct mei_csr *csr;<br>@@ -543,7 +543,7 @@<br>             path = ME_ERROR_BIOS_PATH;<br>    }<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>  if (path != ME_NORMAL_BIOS_PATH) {<br>            struct elog_event_data_me_extended data = {<br>                   .current_working_state = hfs.working_state,<br>@@ -632,7 +632,7 @@<br>      }<br>     printk(BIOS_DEBUG, "\n");<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br>        /* Save hash in NVS for the OS to verify */<br>   chromeos_set_me_hash(extend, count);<br> #endif<br>diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h<br>index 6d8b873..9ae9467 100644<br>--- a/src/southbridge/intel/fsp_i89xx/pch.h<br>+++ b/src/southbridge/intel/fsp_i89xx/pch.h<br>@@ -65,7 +65,7 @@<br> int pch_silicon_type(void);<br> int pch_silicon_supported(int type, int rev);<br> void pch_enable(device_t dev);<br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br> void pch_log_state(void);<br> #endif<br> #else<br>diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c<br>index c2b5221..385e4d6 100644<br>--- a/src/southbridge/intel/fsp_i89xx/romstage.c<br>+++ b/src/southbridge/intel/fsp_i89xx/romstage.c<br>@@ -137,7 +137,7 @@<br>       pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);<br>      post_code(0x46);<br>      if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {<br>-#if CONFIG_HAVE_ACPI_RESUME<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br>                printk(BIOS_DEBUG, "Resume from S3 detected.\n");<br>           boot_mode = 2;<br>                /* Clear SLP_TYPE. This will break stage2 but<br>diff --git a/src/southbridge/intel/fsp_i89xx/smi.c b/src/southbridge/intel/fsp_i89xx/smi.c<br>index f28d966..6dc58f0 100644<br>--- a/src/southbridge/intel/fsp_i89xx/smi.c<br>+++ b/src/southbridge/intel/fsp_i89xx/smi.c<br>@@ -227,7 +227,7 @@<br>       u16 pm1_en;<br>   u32 gpe0_en;<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>       /* Log events from chipset before clearing */<br>         pch_log_state();<br> #endif<br>diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c<br>index 099fb84..ff76c20 100644<br>--- a/src/southbridge/intel/fsp_i89xx/smihandler.c<br>+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c<br>@@ -331,7 +331,7 @@<br>       /* Do any mainboard sleep handling */<br>         mainboard_smi_sleep(slp_typ);<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>    /* Log S3, S4, and S5 entry */<br>        if (slp_typ >= ACPI_S3)<br>            elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);<br>@@ -433,7 +433,7 @@<br>      return NULL;<br> }<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> static void southbridge_smi_gsmi(void)<br> {<br>    u32 *ret, *param;<br>@@ -505,7 +505,7 @@<br>                        printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);<br>             }<br>             break;<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>      case ELOG_GSMI_APM_CNT:<br>               southbridge_smi_gsmi();<br>               break;<br>@@ -529,7 +529,7 @@<br>           // power button pressed<br>               u32 reg32;<br>            reg32 = (7 << 10) | (1 << 13);<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>          elog_add_event(ELOG_TYPE_POWER_BUTTON);<br> #endif<br>              outl(reg32, pmbase + PM1_CNT);<br>diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c<br>index d621a41..cbb2297 100644<br>--- a/src/southbridge/intel/fsp_rangeley/lpc.c<br>+++ b/src/southbridge/intel/fsp_rangeley/lpc.c<br>@@ -94,7 +94,7 @@<br>    /* Set packet length and toggle silent mode bit for one frame. */<br>     write8(ibase + ILB_SERIRQ_CNTL, (1 << 7));<br> <br>-#if !CONFIG_SERIRQ_CONTINUOUS_MODE<br>+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)<br>     write8(ibase + ILB_SERIRQ_CNTL, 0);<br> #endif<br> }<br>@@ -435,7 +435,7 @@<br>                 memset(gnvs, 0, sizeof(*gnvs));<br>               acpi_create_gnvs(gnvs);<br>               acpi_save_gnvs((unsigned long)gnvs);<br>-#if CONFIG_HAVE_SMI_HANDLER<br>+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br>          /* And tell SMI about it */<br>           smm_setup_structures(gnvs, NULL, NULL);<br> #endif<br>diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h<br>index 0674dca..4409f1e 100644<br>--- a/src/southbridge/intel/fsp_rangeley/soc.h<br>+++ b/src/southbridge/intel/fsp_rangeley/soc.h<br>@@ -65,7 +65,7 @@<br> #include <arch/acpi.h><br> void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt);<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br> void soc_log_state(void);<br> #endif<br> #else<br>diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c<br>index bd0e964..2bab05c 100644<br>--- a/src/southbridge/intel/i82371eb/isa.c<br>+++ b/src/southbridge/intel/i82371eb/isa.c<br>@@ -28,7 +28,7 @@<br> #endif<br> #include "i82371eb.h"<br> <br>-#if CONFIG_IOAPIC<br>+#if IS_ENABLED(CONFIG_IOAPIC)<br> static void enable_intel_82093aa_ioapic(void)<br> {<br>   u16 reg16;<br>@@ -84,7 +84,7 @@<br>         /* Initialize ISA DMA. */<br>     isa_dma_init();<br> <br>-#if CONFIG_IOAPIC<br>+#if IS_ENABLED(CONFIG_IOAPIC)<br>        /*<br>     * Unlike most other southbridges the 82371EB doesn't have a built-in<br>      * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs<br>@@ -115,7 +115,7 @@<br>      res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |<br>             IORESOURCE_RESERVE;<br> <br>-#if CONFIG_IOAPIC<br>+#if IS_ENABLED(CONFIG_IOAPIC)<br>    res = new_resource(dev, 3); /* IOAPIC */<br>      res->base = IO_APIC_ADDR;<br>  res->size = 0x00001000;<br>diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c<br>index e650d82..a26b9f8 100644<br>--- a/src/southbridge/intel/i82801gx/lpc.c<br>+++ b/src/southbridge/intel/i82801gx/lpc.c<br>@@ -329,7 +329,7 @@<br>      RCBA32(CG) = reg32;<br> }<br> <br>-#if CONFIG_HAVE_SMI_HANDLER<br>+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br> static void i82801gx_lock_smm(struct device *dev)<br> {<br> #if TEST_SMM_FLASH_LOCKDOWN<br>@@ -448,7 +448,7 @@<br>         /* Interrupt 9 should be level triggered (SCI) */<br>     i8259_configure_irq_trigger(9, 1);<br> <br>-#if CONFIG_HAVE_SMI_HANDLER<br>+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br>         i82801gx_lock_smm(dev);<br> #endif<br> <br>diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c<br>index 6bd9517..d3c32fd 100644<br>--- a/src/southbridge/intel/i82801gx/smihandler.c<br>+++ b/src/southbridge/intel/i82801gx/smihandler.c<br>@@ -414,7 +414,7 @@<br>                 printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;<br>       }<br> <br>-#if !CONFIG_SMM_TSEG<br>+#if !IS_ENABLED(CONFIG_SMM_TSEG)<br>        /* Unlock the SMI semaphore. We're currently in SMM, and the semaphore<br>     * will never be unlocked because the next outl will switch off the CPU.<br>       * This might open a small race between the smi_release_lock() and the outl()<br>diff --git a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl<br>index 62bb026..d7fb2a5 100644<br>--- a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl<br>+++ b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl<br>@@ -15,7 +15,7 @@<br>  */<br> <br> Name(\_S0, Package(){0x0,0x0,0x0,0x0})<br>-#if !CONFIG_HAVE_ACPI_RESUME<br>+#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> Name(\_S1, Package(){0x1,0x0,0x0,0x0})<br> #else<br> Name(\_S3, Package(){0x5,0x0,0x0,0x0})<br>diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c<br>index 0f3a08c..7d44fba 100644<br>--- a/src/southbridge/intel/i82801ix/i82801ix.c<br>+++ b/src/southbridge/intel/i82801ix/i82801ix.c<br>@@ -222,7 +222,7 @@<br>         i82801ix_hide_functions();<br> <br>         /* Reset watchdog timer. */<br>-#if !CONFIG_HAVE_SMI_HANDLER<br>+#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br>         outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */<br> #endif<br>  outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */<br>diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c<br>index 8212b0a..bc45b9d 100644<br>--- a/src/southbridge/intel/i82801ix/lpc.c<br>+++ b/src/southbridge/intel/i82801ix/lpc.c<br>@@ -369,7 +369,7 @@<br>       RCBA32(0x38c0) |= 7;<br> }<br> <br>-#if CONFIG_HAVE_SMI_HANDLER<br>+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br> static void i82801ix_lock_smm(struct device *dev)<br> {<br> #if TEST_SMM_FLASH_LOCKDOWN<br>@@ -464,7 +464,7 @@<br>        /* Interrupt 9 should be level triggered (SCI) */<br>     i8259_configure_irq_trigger(9, 1);<br> <br>-#if CONFIG_HAVE_SMI_HANDLER<br>+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br>         i82801ix_lock_smm(dev);<br> #endif<br> }<br>diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c<br>index f01d8b2..a152dfe 100644<br>--- a/src/southbridge/intel/ibexpeak/lpc.c<br>+++ b/src/southbridge/intel/ibexpeak/lpc.c<br>@@ -71,7 +71,7 @@<br>      /* Set packet length and toggle silent mode bit for one frame. */<br>     pci_write_config8(dev, SERIRQ_CNTL,<br>                     (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));<br>-#if !CONFIG_SERIRQ_CONTINUOUS_MODE<br>+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)<br>   pci_write_config8(dev, SERIRQ_CNTL,<br>                     (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));<br> #endif<br>@@ -280,7 +280,7 @@<br>   if (rtc_failed) {<br>             reg8 &= ~RTC_BATTERY_DEAD;<br>                pci_write_config8(dev, GEN_PMCON_3, reg8);<br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>            elog_add_event(ELOG_TYPE_RTC_RESET);<br> #endif<br>         }<br>diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c<br>index da6bfa8..70dbcbf 100644<br>--- a/src/southbridge/intel/ibexpeak/me.c<br>+++ b/src/southbridge/intel/ibexpeak/me.c<br>@@ -41,7 +41,7 @@<br> #include "me.h"<br> #include "pch.h"<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> #include <vendorcode/google/chromeos/gnvs.h><br> #endif<br> <br>@@ -60,7 +60,7 @@<br> /* MMIO base address for MEI interface */<br> static u32 *mei_base_address;<br> <br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br> static void mei_dump(void *ptr, int dword, int offset, const char *type)<br> {<br>   struct mei_csr *csr;<br>@@ -470,7 +470,7 @@<br>     if (hfs.error_code || hfs.fpt_bad)<br>            path = ME_ERROR_BIOS_PATH;<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>         if (path != ME_NORMAL_BIOS_PATH) {<br>            struct elog_event_data_me_extended data = {<br>                   .current_working_state = hfs.working_state,<br>@@ -559,7 +559,7 @@<br>      }<br>     printk(BIOS_DEBUG, "\n");<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br>        /* Save hash in NVS for the OS to verify */<br>   chromeos_set_me_hash(extend, count);<br> #endif<br>diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h<br>index d87f8e0..63307d9 100644<br>--- a/src/southbridge/intel/ibexpeak/pch.h<br>+++ b/src/southbridge/intel/ibexpeak/pch.h<br>@@ -70,7 +70,7 @@<br> int pch_silicon_supported(int type, int rev);<br> void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);<br> void gpi_route_interrupt(u8 gpi, u8 mode);<br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br> void pch_log_state(void);<br> #endif<br> #else /* __PRE_RAM__ */<br>diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c<br>index 950dbe0..f1bcf03 100644<br>--- a/src/southbridge/intel/ibexpeak/smi.c<br>+++ b/src/southbridge/intel/ibexpeak/smi.c<br>@@ -228,7 +228,7 @@<br>   u16 pm1_en;<br>   u32 gpe0_en;<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>       /* Log events from chipset before clearing */<br>         pch_log_state();<br> #endif<br>diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c<br>index a0b963e..88f64f1 100644<br>--- a/src/southbridge/intel/ibexpeak/smihandler.c<br>+++ b/src/southbridge/intel/ibexpeak/smihandler.c<br>@@ -433,7 +433,7 @@<br>   /* Do any mainboard sleep handling */<br>         mainboard_smi_sleep(slp_typ);<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>    /* Log S3, S4, and S5 entry */<br>        if (slp_typ >= ACPI_S3)<br>            elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);<br>@@ -535,7 +535,7 @@<br>      return NULL;<br> }<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> static void southbridge_smi_gsmi(void)<br> {<br>    u32 *ret, *param;<br>@@ -607,7 +607,7 @@<br>                        printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);<br>             }<br>             break;<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>      case ELOG_GSMI_APM_CNT:<br>               southbridge_smi_gsmi();<br>               break;<br>@@ -631,7 +631,7 @@<br>           // power button pressed<br>               u32 reg32;<br>            reg32 = (7 << 10) | (1 << 13);<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>          elog_add_event(ELOG_TYPE_POWER_BUTTON);<br> #endif<br>              outl(reg32, pmbase + PM1_CNT);<br>diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl<br>index c30bfa4..fbbd26d 100644<br>--- a/src/southbridge/intel/lynxpoint/acpi/pch.asl<br>+++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl<br>@@ -96,7 +96,7 @@<br> #include "smbus.asl"<br> <br> // Serial IO<br>-#if CONFIG_INTEL_LYNXPOINT_LP<br>+#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)<br> #include "serialio.asl"<br> #include "lpt_lp.asl"<br> #endif<br>diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c<br>index 0e4fa3d..cb4bc7e 100644<br>--- a/src/southbridge/intel/lynxpoint/early_pch.c<br>+++ b/src/southbridge/intel/lynxpoint/early_pch.c<br>@@ -24,7 +24,7 @@<br> #include "pch.h"<br> #include "chip.h"<br> <br>-#if CONFIG_INTEL_LYNXPOINT_LP<br>+#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)<br> #include "lp_gpio.h"<br> #else<br> #include "southbridge/intel/common/gpio.h"<br>@@ -133,7 +133,7 @@<br> <br>    pch_enable_bars();<br> <br>-#if CONFIG_INTEL_LYNXPOINT_LP<br>+#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)<br>     setup_pch_lp_gpios(gpio_map);<br> #else<br>         setup_pch_gpios(gpio_map);<br>@@ -154,7 +154,7 @@<br> <br>    wake_from_s3 = sleep_type_s3();<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br>      if (!wake_from_s3)<br>            boot_count_increment();<br> #endif<br>diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c<br>index 1ff38e9..39a555e 100644<br>--- a/src/southbridge/intel/lynxpoint/finalize.c<br>+++ b/src/southbridge/intel/lynxpoint/finalize.c<br>@@ -34,7 +34,7 @@<br>  /* Lock SPIBAR */<br>     RCBA32_OR(0x3804, (1 << 15));<br> <br>-#if CONFIG_SPI_FLASH_SMM<br>+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)<br>      /* Re-init SPI driver to handle locked BAR */<br>         spi_init();<br> #endif<br>diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c<br>index d295c88..55edaf9 100644<br>--- a/src/southbridge/intel/lynxpoint/lpc.c<br>+++ b/src/southbridge/intel/lynxpoint/lpc.c<br>@@ -77,7 +77,7 @@<br>  /* Set packet length and toggle silent mode bit for one frame. */<br>     pci_write_config8(dev, SERIRQ_CNTL,<br>                     (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));<br>-#if !CONFIG_SERIRQ_CONTINUOUS_MODE<br>+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)<br>   pci_write_config8(dev, SERIRQ_CNTL,<br>                     (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));<br> #endif<br>@@ -292,7 +292,7 @@<br>   if (rtc_failed) {<br>             reg8 &= ~RTC_BATTERY_DEAD;<br>                pci_write_config8(dev, GEN_PMCON_3, reg8);<br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>            elog_add_event(ELOG_TYPE_RTC_RESET);<br> #endif<br>         }<br>@@ -498,7 +498,7 @@<br> <br> static void pch_set_acpi_mode(void)<br> {<br>-#if CONFIG_HAVE_SMI_HANDLER<br>+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br>   if (!acpi_is_wakeup_s3()) {<br> #if ENABLE_ACPI_MODE_IN_COREBOOT<br>                printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");<br>@@ -760,7 +760,7 @@<br>               gnvs->mpen = 1; /* Enable Multi Processing */<br>              gnvs->pcnt = dev_count_cpu();<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br>           chromeos_init_vboot(&(gnvs->chromeos));<br> #endif<br> <br>diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c<br>index 355db4b..c393feb 100644<br>--- a/src/southbridge/intel/lynxpoint/me_9.x.c<br>+++ b/src/southbridge/intel/lynxpoint/me_9.x.c<br>@@ -37,7 +37,7 @@<br> #include "me.h"<br> #include "pch.h"<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> #include <vendorcode/google/chromeos/chromeos.h><br> #include <vendorcode/google/chromeos/gnvs.h><br> #endif<br>@@ -59,7 +59,7 @@<br> static u32 *mei_base_address;<br> void intel_me_mbp_clear(device_t dev);<br> <br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br> static void mei_dump(void *ptr, int dword, int offset, const char *type)<br> {<br>   struct mei_csr *csr;<br>@@ -519,7 +519,7 @@<br> #endif /* CONFIG_DEBUG_INTEL_ME */<br> #endif<br> <br>-#if CONFIG_CHROMEOS && 0 /* DISABLED */<br>+#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */<br> /* Tell ME to issue a global reset */<br> static int mkhi_global_reset(void)<br> {<br>@@ -579,7 +579,7 @@<br>      if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)<br>               return;<br> <br>-#if CONFIG_ME_MBP_CLEAR_LATE<br>+#if IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE)<br>  /* Wait for ME MBP Cleared indicator */<br>       intel_me_mbp_clear(PCH_ME_DEV);<br> #endif<br>@@ -707,7 +707,7 @@<br>                 path = ME_ERROR_BIOS_PATH;<br>    }<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>  if (path != ME_NORMAL_BIOS_PATH) {<br>            struct elog_event_data_me_extended data = {<br>                   .current_working_state = hfs.working_state,<br>@@ -796,7 +796,7 @@<br>      }<br>     printk(BIOS_DEBUG, "\n");<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br>        /* Save hash in NVS for the OS to verify */<br>   chromeos_set_me_hash(extend, count);<br> #endif<br>@@ -835,7 +835,7 @@<br> <br> #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)<br>        me_print_fw_version(mbp_data.fw_version_name);<br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br>    me_print_fwcaps(mbp_data.fw_capabilities);<br> #endif<br> <br>@@ -991,7 +991,7 @@<br>   host.interrupt_generate = 1;<br>  write_host_csr(&host);<br> <br>-#if !CONFIG_ME_MBP_CLEAR_LATE<br>+#if !IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE)<br>     /* Wait for the mbp_cleared indicator. */<br>     intel_me_mbp_clear(dev);<br> #endif<br>@@ -1000,7 +1000,7 @@<br> #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)<br>     printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",<br>              mbp->header.num_entries, mbp->header.mbp_size);<br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br>      for (i = 0; i < mbp->header.mbp_size - 1; i++) {<br>                printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]);<br>    }<br>diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h<br>index 8cae50a..9b061c6 100644<br>--- a/src/southbridge/intel/lynxpoint/pch.h<br>+++ b/src/southbridge/intel/lynxpoint/pch.h<br>@@ -72,7 +72,7 @@<br> #define SMBUS_IO_BASE               0x0400<br> #define SMBUS_SLAVE_ADDR       0x24<br> <br>-#if CONFIG_INTEL_LYNXPOINT_LP<br>+#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)<br> #define DEFAULT_PMBASE            0x1000<br> #define DEFAULT_GPIOBASE       0x1400<br> #define DEFAULT_GPIOSIZE       0x400<br>@@ -181,7 +181,7 @@<br> u32 pch_iobp_read(u32 address);<br> void pch_iobp_write(u32 address, u32 data);<br> void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);<br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br> void pch_log_state(void);<br> #endif<br> void acpi_create_intel_hpet(acpi_hpet_t * hpet);<br>diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c<br>index 90045d1..d70cb5d 100644<br>--- a/src/southbridge/intel/lynxpoint/pmutil.c<br>+++ b/src/southbridge/intel/lynxpoint/pmutil.c<br>@@ -26,7 +26,7 @@<br> #include <console/console.h><br> #include "pch.h"<br> <br>-#if CONFIG_INTEL_LYNXPOINT_LP<br>+#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)<br> #include "lp_gpio.h"<br> #endif<br> <br>diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c<br>index 8c9cb58..5f1bdf7 100644<br>--- a/src/southbridge/intel/lynxpoint/smi.c<br>+++ b/src/southbridge/intel/lynxpoint/smi.c<br>@@ -29,7 +29,7 @@<br> {<br>      u32 smi_en;<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br>        /* Log events from chipset before clearing */<br>         pch_log_state();<br> #endif<br>@@ -123,7 +123,7 @@<br> /*<br>  * Finalize system before payload boot if not in ChromeOS environment.<br>  */<br>-#if !CONFIG_CHROMEOS<br>+#if !IS_ENABLED(CONFIG_CHROMEOS)<br> <br> static void finalize_boot(void *unused)<br> {<br>diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c<br>index 0102308..37a7a2b 100644<br>--- a/src/southbridge/intel/lynxpoint/smihandler.c<br>+++ b/src/southbridge/intel/lynxpoint/smihandler.c<br>@@ -130,13 +130,13 @@<br>         mainboard_smi_sleep(slp_typ);<br> <br>      /* USB sleep preparations */<br>-#if !CONFIG_FINALIZE_USB_ROUTE_XHCI<br>+#if !IS_ENABLED(CONFIG_FINALIZE_USB_ROUTE_XHCI)<br>  usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ);<br>       usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ);<br> #endif<br>      usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ);<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>   /* Log S3, S4, and S5 entry */<br>        if (slp_typ >= ACPI_S3)<br>            elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);<br>@@ -243,7 +243,7 @@<br>      return NULL;<br> }<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> static void southbridge_smi_gsmi(void)<br> {<br>    u32 *ret, *param;<br>@@ -314,7 +314,7 @@<br>        case 0xca:<br>            usb_xhci_route_all();<br>                 break;<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>      case ELOG_GSMI_APM_CNT:<br>               southbridge_smi_gsmi();<br>               break;<br>@@ -333,7 +333,7 @@<br>    */<br>   if (pm1_sts & PWRBTN_STS) {<br>               // power button pressed<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br>             elog_add_event(ELOG_TYPE_POWER_BUTTON);<br> #endif<br>              disable_pm1_control(-1UL);<br></pre><p>To view, visit <a href="https://review.coreboot.org/20350">change 20350</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20350"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45 </div>
<div style="display:none"> Gerrit-Change-Number: 20350 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>