[coreboot-gerrit] Change in coreboot[master]: soc/intel: add IS_ENABLED() around Kconfig symbol references
Martin Roth (Code Review)
gerrit at coreboot.org
Sun Jun 25 21:07:00 CEST 2017
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20348
Change subject: soc/intel: add IS_ENABLED() around Kconfig symbol references
......................................................................
soc/intel: add IS_ENABLED() around Kconfig symbol references
Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/soc/intel/baytrail/acpi.c
M src/soc/intel/baytrail/include/soc/pmc.h
M src/soc/intel/baytrail/include/soc/ramstage.h
M src/soc/intel/baytrail/include/soc/romstage.h
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/baytrail/smihandler.c
M src/soc/intel/baytrail/spi.c
M src/soc/intel/broadwell/acpi.c
M src/soc/intel/broadwell/include/soc/ramstage.h
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/romstage/raminit.c
M src/soc/intel/broadwell/romstage/romstage.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/broadwell/smihandler.c
M src/soc/intel/broadwell/spi.c
M src/soc/intel/common/acpi/acpi_debug.asl
M src/soc/intel/fsp_baytrail/acpi/sleepstates.asl
19 files changed, 45 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/20348/1
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index 39ffa20..b3f5ea6 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -85,15 +85,15 @@
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();
-#if CONFIG_CONSOLE_CBMEM
+#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
/* Update the mem console pointer. */
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
#endif
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
/* Initialize Verified Boot data */
chromeos_init_vboot(&(gnvs->chromeos));
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h
index c8d6a67..38136ec 100644
--- a/src/soc/intel/baytrail/include/soc/pmc.h
+++ b/src/soc/intel/baytrail/include/soc/pmc.h
@@ -281,7 +281,7 @@
void disable_gpe(uint32_t mask);
void disable_all_gpe(void);
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
void southcluster_log_state(void);
#else
static inline void southcluster_log_state(void) {}
diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h
index 824df74..083bf77 100644
--- a/src/soc/intel/baytrail/include/soc/ramstage.h
+++ b/src/soc/intel/baytrail/include/soc/ramstage.h
@@ -25,7 +25,7 @@
void baytrail_init_cpus(device_t dev);
void set_max_freq(void);
void southcluster_enable_dev(device_t dev);
-#if CONFIG_HAVE_REFCODE_BLOB
+#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)
void baytrail_run_reference_code(void);
#else
static inline void baytrail_run_reference_code(void) {}
diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h
index 7913c20..a3f1fc7 100644
--- a/src/soc/intel/baytrail/include/soc/romstage.h
+++ b/src/soc/intel/baytrail/include/soc/romstage.h
@@ -41,7 +41,7 @@
void set_max_freq(void);
int early_spi_read_wpsr(u8 *sr);
-#if CONFIG_ENABLE_BUILTIN_COM1
+#if IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1)
void byt_config_com1_and_enable(void);
#else
static inline void byt_config_com1_and_enable(void) { }
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 190231d..f9a5fd1 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -137,7 +137,7 @@
reset_system();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (prev_sleep_state == ACPI_S0) {
/* Ensure EC is running RO firmware. */
google_chromeec_check_ec_image(EC_IMAGE_RO);
@@ -168,7 +168,7 @@
if (prev_sleep_state != ACPI_S3) {
cbmem_initialize_empty();
} else if (cbmem_initialize()) {
- #if CONFIG_HAVE_ACPI_RESUME
+ #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
reset_system();
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index d457151..b6bc64c 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -21,7 +21,7 @@
#include <cbfs.h>
#include <cbmem.h>
#include <cpu/x86/mtrr.h>
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
#include <ec/google/chromeec/ec.h>
#endif
#include <elog.h>
@@ -128,7 +128,7 @@
gfx_init();
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
#endif
@@ -221,7 +221,7 @@
printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
-#if CONFIG_ELOG_BOOT_COUNT
+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
if (prev_sleep_state != ACPI_S3)
boot_count_increment();
#endif
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index dbd4218..683bf30 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -112,7 +112,7 @@
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -208,7 +208,7 @@
return NULL;
}
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -241,7 +241,7 @@
}
finalize_done = 1;
-#if CONFIG_SPI_FLASH_SMM
+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif
@@ -346,7 +346,7 @@
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@@ -372,7 +372,7 @@
*/
if (pm1_sts & PWRBTN_STS) {
// power button pressed
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
disable_pm1_control(-1UL);
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 6061116..9dd2555 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -162,7 +162,7 @@
SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
};
-#if CONFIG_DEBUG_SPI_FLASH
+#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
static u8 readb_(const void *addr)
{
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 6d20259..a23c8e2 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -169,15 +169,15 @@
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
-#if CONFIG_CONSOLE_CBMEM
+#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
/* Update the mem console pointer. */
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
#endif
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
/* Initialize Verified Boot data */
chromeos_init_vboot(&(gnvs->chromeos));
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h
index db67fe3..1009bba 100644
--- a/src/soc/intel/broadwell/include/soc/ramstage.h
+++ b/src/soc/intel/broadwell/include/soc/ramstage.h
@@ -23,7 +23,7 @@
void broadwell_init_cpus(device_t dev);
void broadwell_pch_enable_dev(device_t dev);
-#if CONFIG_HAVE_REFCODE_BLOB
+#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)
void broadwell_run_reference_code(void);
#else
static inline void broadwell_run_reference_code(void) { }
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 36e34fe..4430e73 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -221,7 +221,7 @@
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)),
/* Setup SERIRQ, enable continuous mode */
REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
-#if !CONFIG_SERIRQ_CONTINUOUS_MODE
+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
#endif
REG_SCRIPT_END
@@ -431,7 +431,7 @@
static void pch_set_acpi_mode(void)
{
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
if (!acpi_is_wakeup_s3()) {
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT);
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 73b3c2e..ed2f728 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -39,7 +39,7 @@
#include <soc/rcba.h>
#include <soc/intel/broadwell/chip.h>
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -57,7 +57,7 @@
/* MMIO base address for MEI interface */
static u8 *mei_base_address;
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -482,7 +482,7 @@
vers_name->hotfix_version, vers_name->build_version);
}
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static inline void print_cap(const char *name, int state)
{
printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n",
@@ -702,7 +702,7 @@
path = ME_ERROR_BIOS_PATH;
}
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -791,7 +791,7 @@
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
@@ -803,7 +803,7 @@
{
me_print_fw_version(mbp_data->fw_version_name);
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
me_print_fwcaps(mbp_data->fw_capabilities);
#endif
@@ -911,7 +911,7 @@
}
/* Dump out the MBP contents. */
-#if CONFIG_DEBUG_INTEL_ME
+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",
mbp->header.num_entries, mbp->header.mbp_size);
for (i = 0; i < mbp->header.mbp_size - 1; i++)
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 10cb733..34ab39c 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -22,7 +22,7 @@
#include <device/pci_def.h>
#include <lib.h>
#include <string.h>
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#endif
@@ -65,7 +65,7 @@
reset_system();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (pei_data->boot_mode == ACPI_S0) {
/* Ensure EC is running RO firmware. */
google_chromeec_check_ec_image(EC_IMAGE_RO);
@@ -110,7 +110,7 @@
if (pei_data->boot_mode != ACPI_S3) {
cbmem_initialize_empty();
} else if (cbmem_initialize()) {
-#if CONFIG_HAVE_ACPI_RESUME
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
reset_system();
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index af95530..b5e5229 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -91,7 +91,7 @@
params->pei_data->boot_mode = params->power_state->prev_sleep_state;
-#if CONFIG_ELOG_BOOT_COUNT
+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
if (params->power_state->prev_sleep_state != ACPI_S3)
boot_count_increment();
#endif
@@ -110,7 +110,7 @@
romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3);
-#if CONFIG_LPC_TPM
+#if IS_ENABLED(CONFIG_LPC_TPM)
init_tpm(params->power_state->prev_sleep_state == ACPI_S3);
#endif
}
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index a73312c..eb70112 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -40,7 +40,7 @@
static int serialio_uart_is_debug(struct device *dev)
{
-#if CONFIG_INTEL_PCH_UART_CONSOLE
+#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)
switch (dev->path.pci.devfn) {
case PCH_DEVFN_UART0: /* UART0 */
return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0);
@@ -277,7 +277,7 @@
{
pci_dev_set_resources(dev);
-#if CONFIG_INTEL_PCH_UART_CONSOLE
+#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)
/* Update UART base address if used for debug */
if (serialio_uart_is_debug(dev)) {
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 8a5b443..0b8a970 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -176,7 +176,7 @@
/* USB sleep preparations */
usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ);
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -290,7 +290,7 @@
return NULL;
}
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -323,7 +323,7 @@
}
finalize_done = 1;
-#if CONFIG_SPI_FLASH_SMM
+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif
@@ -369,7 +369,7 @@
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@@ -388,7 +388,7 @@
*/
if (pm1_sts & PWRBTN_STS) {
/* power button pressed */
-#if CONFIG_ELOG_GSMI
+#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
disable_pm1_control(-1UL);
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index a573e32..b27ad23 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -161,7 +161,7 @@
SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
};
-#if CONFIG_DEBUG_SPI_FLASH
+#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
static u8 readb_(const void *addr)
{
diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl
index 76805fe..aa7a1af 100644
--- a/src/soc/intel/common/acpi/acpi_debug.asl
+++ b/src/soc/intel/common/acpi/acpi_debug.asl
@@ -57,7 +57,7 @@
}
Store (INDX, LENG) /* Length of the String */
-#if CONFIG_DRIVERS_UART_8250MEM_32
+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)
OperationRegion (UBAR, SystemMemory, UART_DEBUG_BASE_ADDRESS, 24)
Field (UBAR, AnyAcc, NoLock, Preserve)
{
diff --git a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl
index 2001f83..ae958c2 100644
--- a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl
+++ b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl
@@ -16,7 +16,7 @@
Name(\_S0, Package(){0x0,0x0,0x0,0x0})
// Name(\_S1, Package(){0x1,0x1,0x0,0x0})
-#if CONFIG_HAVE_ACPI_RESUME
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
Name(\_S3, Package(){0x5,0x5,0x0,0x0})
#endif
Name(\_S4, Package(){0x6,0x6,0x0,0x0})
--
To view, visit https://review.coreboot.org/20348
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64
Gerrit-Change-Number: 20348
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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