<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20348">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel: add IS_ENABLED() around Kconfig symbol references<br><br>Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/soc/intel/baytrail/acpi.c<br>M src/soc/intel/baytrail/include/soc/pmc.h<br>M src/soc/intel/baytrail/include/soc/ramstage.h<br>M src/soc/intel/baytrail/include/soc/romstage.h<br>M src/soc/intel/baytrail/romstage/raminit.c<br>M src/soc/intel/baytrail/romstage/romstage.c<br>M src/soc/intel/baytrail/smihandler.c<br>M src/soc/intel/baytrail/spi.c<br>M src/soc/intel/broadwell/acpi.c<br>M src/soc/intel/broadwell/include/soc/ramstage.h<br>M src/soc/intel/broadwell/lpc.c<br>M src/soc/intel/broadwell/me.c<br>M src/soc/intel/broadwell/romstage/raminit.c<br>M src/soc/intel/broadwell/romstage/romstage.c<br>M src/soc/intel/broadwell/serialio.c<br>M src/soc/intel/broadwell/smihandler.c<br>M src/soc/intel/broadwell/spi.c<br>M src/soc/intel/common/acpi/acpi_debug.asl<br>M src/soc/intel/fsp_baytrail/acpi/sleepstates.asl<br>19 files changed, 45 insertions(+), 45 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/20348/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c<br>index 39ffa20..b3f5ea6 100644<br>--- a/src/soc/intel/baytrail/acpi.c<br>+++ b/src/soc/intel/baytrail/acpi.c<br>@@ -85,15 +85,15 @@<br> /* Top of Low Memory (start of resource allocation) */<br> gnvs->tolm = nc_read_top_of_low_memory();<br> <br>-#if CONFIG_CONSOLE_CBMEM<br>+#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)<br> /* Update the mem console pointer. */<br> gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);<br> #endif<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> /* Initialize Verified Boot data */<br> chromeos_init_vboot(&(gnvs->chromeos));<br>-#if CONFIG_EC_GOOGLE_CHROMEEC<br>+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)<br> gnvs->chromeos.vbt2 = google_ec_running_ro() ?<br> ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;<br> #endif<br>diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h<br>index c8d6a67..38136ec 100644<br>--- a/src/soc/intel/baytrail/include/soc/pmc.h<br>+++ b/src/soc/intel/baytrail/include/soc/pmc.h<br>@@ -281,7 +281,7 @@<br> void disable_gpe(uint32_t mask);<br> void disable_all_gpe(void);<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br> void southcluster_log_state(void);<br> #else<br> static inline void southcluster_log_state(void) {}<br>diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h<br>index 824df74..083bf77 100644<br>--- a/src/soc/intel/baytrail/include/soc/ramstage.h<br>+++ b/src/soc/intel/baytrail/include/soc/ramstage.h<br>@@ -25,7 +25,7 @@<br> void baytrail_init_cpus(device_t dev);<br> void set_max_freq(void);<br> void southcluster_enable_dev(device_t dev);<br>-#if CONFIG_HAVE_REFCODE_BLOB<br>+#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)<br> void baytrail_run_reference_code(void);<br> #else<br> static inline void baytrail_run_reference_code(void) {}<br>diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h<br>index 7913c20..a3f1fc7 100644<br>--- a/src/soc/intel/baytrail/include/soc/romstage.h<br>+++ b/src/soc/intel/baytrail/include/soc/romstage.h<br>@@ -41,7 +41,7 @@<br> void set_max_freq(void);<br> int early_spi_read_wpsr(u8 *sr);<br> <br>-#if CONFIG_ENABLE_BUILTIN_COM1<br>+#if IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1)<br> void byt_config_com1_and_enable(void);<br> #else<br> static inline void byt_config_com1_and_enable(void) { }<br>diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c<br>index 190231d..f9a5fd1 100644<br>--- a/src/soc/intel/baytrail/romstage/raminit.c<br>+++ b/src/soc/intel/baytrail/romstage/raminit.c<br>@@ -137,7 +137,7 @@<br> reset_system();<br> } else {<br> printk(BIOS_DEBUG, "No MRC cache found.\n");<br>-#if CONFIG_EC_GOOGLE_CHROMEEC<br>+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)<br> if (prev_sleep_state == ACPI_S0) {<br> /* Ensure EC is running RO firmware. */<br> google_chromeec_check_ec_image(EC_IMAGE_RO);<br>@@ -168,7 +168,7 @@<br> if (prev_sleep_state != ACPI_S3) {<br> cbmem_initialize_empty();<br> } else if (cbmem_initialize()) {<br>- #if CONFIG_HAVE_ACPI_RESUME<br>+ #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");<br> /* Failed S3 resume, reset to come up cleanly */<br> reset_system();<br>diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c<br>index d457151..b6bc64c 100644<br>--- a/src/soc/intel/baytrail/romstage/romstage.c<br>+++ b/src/soc/intel/baytrail/romstage/romstage.c<br>@@ -21,7 +21,7 @@<br> #include <cbfs.h><br> #include <cbmem.h><br> #include <cpu/x86/mtrr.h><br>-#if CONFIG_EC_GOOGLE_CHROMEEC<br>+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)<br> #include <ec/google/chromeec/ec.h><br> #endif<br> #include <elog.h><br>@@ -128,7 +128,7 @@<br> <br> gfx_init();<br> <br>-#if CONFIG_EC_GOOGLE_CHROMEEC<br>+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)<br> /* Ensure the EC is in the right mode for recovery */<br> google_chromeec_early_init();<br> #endif<br>@@ -221,7 +221,7 @@<br> <br> printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br> if (prev_sleep_state != ACPI_S3)<br> boot_count_increment();<br> #endif<br>diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c<br>index dbd4218..683bf30 100644<br>--- a/src/soc/intel/baytrail/smihandler.c<br>+++ b/src/soc/intel/baytrail/smihandler.c<br>@@ -112,7 +112,7 @@<br> /* Do any mainboard sleep handling */<br> mainboard_smi_sleep(slp_typ);<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> /* Log S3, S4, and S5 entry */<br> if (slp_typ >= ACPI_S3)<br> elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);<br>@@ -208,7 +208,7 @@<br> return NULL;<br> }<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> static void southbridge_smi_gsmi(void)<br> {<br> u32 *ret, *param;<br>@@ -241,7 +241,7 @@<br> }<br> finalize_done = 1;<br> <br>-#if CONFIG_SPI_FLASH_SMM<br>+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)<br> /* Re-init SPI driver to handle locked BAR */<br> spi_init();<br> #endif<br>@@ -346,7 +346,7 @@<br> printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);<br> }<br> break;<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> case ELOG_GSMI_APM_CNT:<br> southbridge_smi_gsmi();<br> break;<br>@@ -372,7 +372,7 @@<br> */<br> if (pm1_sts & PWRBTN_STS) {<br> // power button pressed<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> elog_add_event(ELOG_TYPE_POWER_BUTTON);<br> #endif<br> disable_pm1_control(-1UL);<br>diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c<br>index 6061116..9dd2555 100644<br>--- a/src/soc/intel/baytrail/spi.c<br>+++ b/src/soc/intel/baytrail/spi.c<br>@@ -162,7 +162,7 @@<br> SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3<br> };<br> <br>-#if CONFIG_DEBUG_SPI_FLASH<br>+#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)<br> <br> static u8 readb_(const void *addr)<br> {<br>diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c<br>index 6d20259..a23c8e2 100644<br>--- a/src/soc/intel/broadwell/acpi.c<br>+++ b/src/soc/intel/broadwell/acpi.c<br>@@ -169,15 +169,15 @@<br> /* CPU core count */<br> gnvs->pcnt = dev_count_cpu();<br> <br>-#if CONFIG_CONSOLE_CBMEM<br>+#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)<br> /* Update the mem console pointer. */<br> gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);<br> #endif<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> /* Initialize Verified Boot data */<br> chromeos_init_vboot(&(gnvs->chromeos));<br>-#if CONFIG_EC_GOOGLE_CHROMEEC<br>+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)<br> gnvs->chromeos.vbt2 = google_ec_running_ro() ?<br> ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;<br> #endif<br>diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h<br>index db67fe3..1009bba 100644<br>--- a/src/soc/intel/broadwell/include/soc/ramstage.h<br>+++ b/src/soc/intel/broadwell/include/soc/ramstage.h<br>@@ -23,7 +23,7 @@<br> void broadwell_init_cpus(device_t dev);<br> void broadwell_pch_enable_dev(device_t dev);<br> <br>-#if CONFIG_HAVE_REFCODE_BLOB<br>+#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)<br> void broadwell_run_reference_code(void);<br> #else<br> static inline void broadwell_run_reference_code(void) { }<br>diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c<br>index 36e34fe..4430e73 100644<br>--- a/src/soc/intel/broadwell/lpc.c<br>+++ b/src/soc/intel/broadwell/lpc.c<br>@@ -221,7 +221,7 @@<br> REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)),<br> /* Setup SERIRQ, enable continuous mode */<br> REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),<br>-#if !CONFIG_SERIRQ_CONTINUOUS_MODE<br>+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)<br> REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),<br> #endif<br> REG_SCRIPT_END<br>@@ -431,7 +431,7 @@<br> <br> static void pch_set_acpi_mode(void)<br> {<br>-#if CONFIG_HAVE_SMI_HANDLER<br>+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br> if (!acpi_is_wakeup_s3()) {<br> printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");<br> outb(APM_CNT_ACPI_DISABLE, APM_CNT);<br>diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c<br>index 73b3c2e..ed2f728 100644<br>--- a/src/soc/intel/broadwell/me.c<br>+++ b/src/soc/intel/broadwell/me.c<br>@@ -39,7 +39,7 @@<br> #include <soc/rcba.h><br> #include <soc/intel/broadwell/chip.h><br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> #include <vendorcode/google/chromeos/chromeos.h><br> #include <vendorcode/google/chromeos/gnvs.h><br> #endif<br>@@ -57,7 +57,7 @@<br> /* MMIO base address for MEI interface */<br> static u8 *mei_base_address;<br> <br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br> static void mei_dump(void *ptr, int dword, int offset, const char *type)<br> {<br> struct mei_csr *csr;<br>@@ -482,7 +482,7 @@<br> vers_name->hotfix_version, vers_name->build_version);<br> }<br> <br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br> static inline void print_cap(const char *name, int state)<br> {<br> printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n",<br>@@ -702,7 +702,7 @@<br> path = ME_ERROR_BIOS_PATH;<br> }<br> <br>-#if CONFIG_ELOG<br>+#if IS_ENABLED(CONFIG_ELOG)<br> if (path != ME_NORMAL_BIOS_PATH) {<br> struct elog_event_data_me_extended data = {<br> .current_working_state = hfs.working_state,<br>@@ -791,7 +791,7 @@<br> }<br> printk(BIOS_DEBUG, "\n");<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> /* Save hash in NVS for the OS to verify */<br> chromeos_set_me_hash(extend, count);<br> #endif<br>@@ -803,7 +803,7 @@<br> {<br> me_print_fw_version(mbp_data->fw_version_name);<br> <br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br> me_print_fwcaps(mbp_data->fw_capabilities);<br> #endif<br> <br>@@ -911,7 +911,7 @@<br> }<br> <br> /* Dump out the MBP contents. */<br>-#if CONFIG_DEBUG_INTEL_ME<br>+#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)<br> printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",<br> mbp->header.num_entries, mbp->header.mbp_size);<br> for (i = 0; i < mbp->header.mbp_size - 1; i++)<br>diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c<br>index 10cb733..34ab39c 100644<br>--- a/src/soc/intel/broadwell/romstage/raminit.c<br>+++ b/src/soc/intel/broadwell/romstage/raminit.c<br>@@ -22,7 +22,7 @@<br> #include <device/pci_def.h><br> #include <lib.h><br> #include <string.h><br>-#if CONFIG_EC_GOOGLE_CHROMEEC<br>+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)<br> #include <ec/google/chromeec/ec.h><br> #include <ec/google/chromeec/ec_commands.h><br> #endif<br>@@ -65,7 +65,7 @@<br> reset_system();<br> } else {<br> printk(BIOS_DEBUG, "No MRC cache found.\n");<br>-#if CONFIG_EC_GOOGLE_CHROMEEC<br>+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)<br> if (pei_data->boot_mode == ACPI_S0) {<br> /* Ensure EC is running RO firmware. */<br> google_chromeec_check_ec_image(EC_IMAGE_RO);<br>@@ -110,7 +110,7 @@<br> if (pei_data->boot_mode != ACPI_S3) {<br> cbmem_initialize_empty();<br> } else if (cbmem_initialize()) {<br>-#if CONFIG_HAVE_ACPI_RESUME<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");<br> /* Failed S3 resume, reset to come up cleanly */<br> reset_system();<br>diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c<br>index af95530..b5e5229 100644<br>--- a/src/soc/intel/broadwell/romstage/romstage.c<br>+++ b/src/soc/intel/broadwell/romstage/romstage.c<br>@@ -91,7 +91,7 @@<br> <br> params->pei_data->boot_mode = params->power_state->prev_sleep_state;<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br> if (params->power_state->prev_sleep_state != ACPI_S3)<br> boot_count_increment();<br> #endif<br>@@ -110,7 +110,7 @@<br> <br> romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3);<br> <br>-#if CONFIG_LPC_TPM<br>+#if IS_ENABLED(CONFIG_LPC_TPM)<br> init_tpm(params->power_state->prev_sleep_state == ACPI_S3);<br> #endif<br> }<br>diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c<br>index a73312c..eb70112 100644<br>--- a/src/soc/intel/broadwell/serialio.c<br>+++ b/src/soc/intel/broadwell/serialio.c<br>@@ -40,7 +40,7 @@<br> <br> static int serialio_uart_is_debug(struct device *dev)<br> {<br>-#if CONFIG_INTEL_PCH_UART_CONSOLE<br>+#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)<br> switch (dev->path.pci.devfn) {<br> case PCH_DEVFN_UART0: /* UART0 */<br> return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0);<br>@@ -277,7 +277,7 @@<br> {<br> pci_dev_set_resources(dev);<br> <br>-#if CONFIG_INTEL_PCH_UART_CONSOLE<br>+#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)<br> /* Update UART base address if used for debug */<br> if (serialio_uart_is_debug(dev)) {<br> struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c<br>index 8a5b443..0b8a970 100644<br>--- a/src/soc/intel/broadwell/smihandler.c<br>+++ b/src/soc/intel/broadwell/smihandler.c<br>@@ -176,7 +176,7 @@<br> /* USB sleep preparations */<br> usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ);<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> /* Log S3, S4, and S5 entry */<br> if (slp_typ >= ACPI_S3)<br> elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);<br>@@ -290,7 +290,7 @@<br> return NULL;<br> }<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> static void southbridge_smi_gsmi(void)<br> {<br> u32 *ret, *param;<br>@@ -323,7 +323,7 @@<br> }<br> finalize_done = 1;<br> <br>-#if CONFIG_SPI_FLASH_SMM<br>+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)<br> /* Re-init SPI driver to handle locked BAR */<br> spi_init();<br> #endif<br>@@ -369,7 +369,7 @@<br> printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);<br> }<br> break;<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> case ELOG_GSMI_APM_CNT:<br> southbridge_smi_gsmi();<br> break;<br>@@ -388,7 +388,7 @@<br> */<br> if (pm1_sts & PWRBTN_STS) {<br> /* power button pressed */<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> elog_add_event(ELOG_TYPE_POWER_BUTTON);<br> #endif<br> disable_pm1_control(-1UL);<br>diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c<br>index a573e32..b27ad23 100644<br>--- a/src/soc/intel/broadwell/spi.c<br>+++ b/src/soc/intel/broadwell/spi.c<br>@@ -161,7 +161,7 @@<br> SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3<br> };<br> <br>-#if CONFIG_DEBUG_SPI_FLASH<br>+#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)<br> <br> static u8 readb_(const void *addr)<br> {<br>diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl<br>index 76805fe..aa7a1af 100644<br>--- a/src/soc/intel/common/acpi/acpi_debug.asl<br>+++ b/src/soc/intel/common/acpi/acpi_debug.asl<br>@@ -57,7 +57,7 @@<br> }<br> Store (INDX, LENG) /* Length of the String */<br> <br>-#if CONFIG_DRIVERS_UART_8250MEM_32<br>+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)<br> OperationRegion (UBAR, SystemMemory, UART_DEBUG_BASE_ADDRESS, 24)<br> Field (UBAR, AnyAcc, NoLock, Preserve)<br> {<br>diff --git a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl<br>index 2001f83..ae958c2 100644<br>--- a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl<br>+++ b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl<br>@@ -16,7 +16,7 @@<br> <br> Name(\_S0, Package(){0x0,0x0,0x0,0x0})<br> // Name(\_S1, Package(){0x1,0x1,0x0,0x0})<br>-#if CONFIG_HAVE_ACPI_RESUME<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> Name(\_S3, Package(){0x5,0x5,0x0,0x0})<br> #endif<br> Name(\_S4, Package(){0x6,0x6,0x0,0x0})<br></pre><p>To view, visit <a href="https://review.coreboot.org/20348">change 20348</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20348"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64 </div>
<div style="display:none"> Gerrit-Change-Number: 20348 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>