[coreboot-gerrit] Change in coreboot[master]: sb/intel/*/smi: Fix ACPI TRAP
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Sun Jun 25 09:53:23 CEST 2017
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20328
Change subject: sb/intel/*/smi: Fix ACPI TRAP
......................................................................
sb/intel/*/smi: Fix ACPI TRAP
Configure the last IO TRAP register on all southbridges
to allow ACPI TRAP to function.
Only on Lenovo T60/X60 this was done, as the docking code
was only ever tested on this board and relies on the ACPI
trap mechanism.
I skipped i82801dx as it doesn't have RCBA.
Tested on Lenovo T500.
Change-Id: I14c9cee3da0dac7428b24c049e68b95ce099322f
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/southbridge/intel/bd82x6x/smi.c
M src/southbridge/intel/fsp_bd82x6x/smi.c
M src/southbridge/intel/fsp_i89xx/pch.h
M src/southbridge/intel/fsp_i89xx/smi.c
M src/southbridge/intel/i82801gx/smi.c
M src/southbridge/intel/ibexpeak/smi.c
M src/southbridge/intel/lynxpoint/smi.c
7 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/20328/1
diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c
index c7cb146..081072f 100644
--- a/src/southbridge/intel/bd82x6x/smi.c
+++ b/src/southbridge/intel/bd82x6x/smi.c
@@ -267,6 +267,7 @@
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
+ * - on ACPI TRAP method
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
*/
@@ -293,6 +294,10 @@
smi_en |= EOS | GBL_SMI_EN;
outl(smi_en, pmbase + SMI_EN);
+
+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+ RCBA32(IOTR3+4) = 0x000200f0;
+ RCBA32(IOTR3+0) = 0x000c0801;
}
void southbridge_trigger_smi(void)
diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c
index d97801e..f2f9701 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smi.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smi.c
@@ -267,6 +267,7 @@
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
+ * - on ACPI TRAP method
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
*/
@@ -293,6 +294,10 @@
smi_en |= EOS | GBL_SMI_EN;
outl(smi_en, pmbase + SMI_EN);
+
+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+ RCBA32(IOTR3+4) = 0x000200f0;
+ RCBA32(IOTR3+0) = 0x000c0801;
}
void southbridge_trigger_smi(void)
diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h
index 6d8b873..513cb7f 100644
--- a/src/southbridge/intel/fsp_i89xx/pch.h
+++ b/src/southbridge/intel/fsp_i89xx/pch.h
@@ -233,6 +233,11 @@
#define TRCR 0x1e10 /* 64bit */
#define TWDR 0x1e18 /* 64bit */
+#define IOTR0 0x1e80 /* 64bit */
+#define IOTR1 0x1e88 /* 64bit */
+#define IOTR2 0x1e90 /* 64bit */
+#define IOTR3 0x1e98 /* 64bit */
+
#define TCTL 0x3000 /* 8bit */
/* IO Buffer Programming */
diff --git a/src/southbridge/intel/fsp_i89xx/smi.c b/src/southbridge/intel/fsp_i89xx/smi.c
index f28d966..66adb66 100644
--- a/src/southbridge/intel/fsp_i89xx/smi.c
+++ b/src/southbridge/intel/fsp_i89xx/smi.c
@@ -267,6 +267,7 @@
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
+ * - on ACPI TRAP method
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
*/
@@ -293,6 +294,10 @@
smi_en |= EOS | GBL_SMI_EN;
outl(smi_en, pmbase + SMI_EN);
+
+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+ RCBA32(IOTR3+4) = 0x000200f0;
+ RCBA32(IOTR3+0) = 0x000c0801;
}
void southbridge_trigger_smi(void)
diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c
index 45fcb10..bfb24ad 100644
--- a/src/southbridge/intel/i82801gx/smi.c
+++ b/src/southbridge/intel/i82801gx/smi.c
@@ -321,6 +321,7 @@
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
+ * - on ACPI TRAP method
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
*/
@@ -351,6 +352,10 @@
pm1_en |= GBL_EN;
outw(pm1_en, pmbase + PM1_EN);
+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+ RCBA32(IOTR3+4) = 0x000200f0;
+ RCBA32(IOTR3+0) = 0x000c0801;
+
/**
* There are several methods of raising a controlled SMI# via
* software, among them:
diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c
index 950dbe0..64065ae 100644
--- a/src/southbridge/intel/ibexpeak/smi.c
+++ b/src/southbridge/intel/ibexpeak/smi.c
@@ -268,6 +268,7 @@
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
+ * - on ACPI TRAP method
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
*/
@@ -294,6 +295,10 @@
smi_en |= EOS | GBL_SMI_EN;
outl(smi_en, pmbase + SMI_EN);
+
+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+ RCBA32(IOTR3+4) = 0x000200f0;
+ RCBA32(IOTR3+0) = 0x000c0801;
}
void southbridge_trigger_smi(void)
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index 8c9cb58..fffb1d9 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -62,11 +62,16 @@
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
+ * - on ACPI TRAP method
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
* - on TCO events
*/
enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
+
+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+ RCBA32(IOTR3+4) = 0x000200f0;
+ RCBA32(IOTR3+0) = 0x000c0801;
}
void southbridge_trigger_smi(void)
--
To view, visit https://review.coreboot.org/20328
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I14c9cee3da0dac7428b24c049e68b95ce099322f
Gerrit-Change-Number: 20328
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
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