<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20328">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/*/smi: Fix ACPI TRAP<br><br>Configure the last IO TRAP register on all southbridges<br>to allow ACPI TRAP to function.<br><br>Only on Lenovo T60/X60 this was done, as the docking code<br>was only ever tested on this board and relies on the ACPI<br>trap mechanism.<br><br>I skipped i82801dx as it doesn't have RCBA.<br><br>Tested on Lenovo T500.<br><br>Change-Id: I14c9cee3da0dac7428b24c049e68b95ce099322f<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/southbridge/intel/bd82x6x/smi.c<br>M src/southbridge/intel/fsp_bd82x6x/smi.c<br>M src/southbridge/intel/fsp_i89xx/pch.h<br>M src/southbridge/intel/fsp_i89xx/smi.c<br>M src/southbridge/intel/i82801gx/smi.c<br>M src/southbridge/intel/ibexpeak/smi.c<br>M src/southbridge/intel/lynxpoint/smi.c<br>7 files changed, 35 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/20328/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c<br>index c7cb146..081072f 100644<br>--- a/src/southbridge/intel/bd82x6x/smi.c<br>+++ b/src/southbridge/intel/bd82x6x/smi.c<br>@@ -267,6 +267,7 @@<br> * - on APMC writes (io 0xb2)<br> * - on writes to SLP_EN (sleep states)<br> * - on writes to GBL_RLS (bios commands)<br>+ * - on ACPI TRAP method<br> * No SMIs:<br> * - on microcontroller writes (io 0x62/0x66)<br> */<br>@@ -293,6 +294,10 @@<br> smi_en |= EOS | GBL_SMI_EN;<br> <br> outl(smi_en, pmbase + SMI_EN);<br>+<br>+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */<br>+ RCBA32(IOTR3+4) = 0x000200f0;<br>+ RCBA32(IOTR3+0) = 0x000c0801;<br> }<br> <br> void southbridge_trigger_smi(void)<br>diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c<br>index d97801e..f2f9701 100644<br>--- a/src/southbridge/intel/fsp_bd82x6x/smi.c<br>+++ b/src/southbridge/intel/fsp_bd82x6x/smi.c<br>@@ -267,6 +267,7 @@<br> * - on APMC writes (io 0xb2)<br> * - on writes to SLP_EN (sleep states)<br> * - on writes to GBL_RLS (bios commands)<br>+ * - on ACPI TRAP method<br> * No SMIs:<br> * - on microcontroller writes (io 0x62/0x66)<br> */<br>@@ -293,6 +294,10 @@<br> smi_en |= EOS | GBL_SMI_EN;<br> <br> outl(smi_en, pmbase + SMI_EN);<br>+<br>+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */<br>+ RCBA32(IOTR3+4) = 0x000200f0;<br>+ RCBA32(IOTR3+0) = 0x000c0801;<br> }<br> <br> void southbridge_trigger_smi(void)<br>diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h<br>index 6d8b873..513cb7f 100644<br>--- a/src/southbridge/intel/fsp_i89xx/pch.h<br>+++ b/src/southbridge/intel/fsp_i89xx/pch.h<br>@@ -233,6 +233,11 @@<br> #define TRCR 0x1e10 /* 64bit */<br> #define TWDR 0x1e18 /* 64bit */<br> <br>+#define IOTR0 0x1e80 /* 64bit */<br>+#define IOTR1 0x1e88 /* 64bit */<br>+#define IOTR2 0x1e90 /* 64bit */<br>+#define IOTR3 0x1e98 /* 64bit */<br>+<br> #define TCTL 0x3000 /* 8bit */<br> <br> /* IO Buffer Programming */<br>diff --git a/src/southbridge/intel/fsp_i89xx/smi.c b/src/southbridge/intel/fsp_i89xx/smi.c<br>index f28d966..66adb66 100644<br>--- a/src/southbridge/intel/fsp_i89xx/smi.c<br>+++ b/src/southbridge/intel/fsp_i89xx/smi.c<br>@@ -267,6 +267,7 @@<br> * - on APMC writes (io 0xb2)<br> * - on writes to SLP_EN (sleep states)<br> * - on writes to GBL_RLS (bios commands)<br>+ * - on ACPI TRAP method<br> * No SMIs:<br> * - on microcontroller writes (io 0x62/0x66)<br> */<br>@@ -293,6 +294,10 @@<br> smi_en |= EOS | GBL_SMI_EN;<br> <br> outl(smi_en, pmbase + SMI_EN);<br>+<br>+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */<br>+ RCBA32(IOTR3+4) = 0x000200f0;<br>+ RCBA32(IOTR3+0) = 0x000c0801;<br> }<br> <br> void southbridge_trigger_smi(void)<br>diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c<br>index 45fcb10..bfb24ad 100644<br>--- a/src/southbridge/intel/i82801gx/smi.c<br>+++ b/src/southbridge/intel/i82801gx/smi.c<br>@@ -321,6 +321,7 @@<br> * - on APMC writes (io 0xb2)<br> * - on writes to SLP_EN (sleep states)<br> * - on writes to GBL_RLS (bios commands)<br>+ * - on ACPI TRAP method<br> * No SMIs:<br> * - on microcontroller writes (io 0x62/0x66)<br> */<br>@@ -351,6 +352,10 @@<br> pm1_en |= GBL_EN;<br> outw(pm1_en, pmbase + PM1_EN);<br> <br>+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */<br>+ RCBA32(IOTR3+4) = 0x000200f0;<br>+ RCBA32(IOTR3+0) = 0x000c0801;<br>+<br> /**<br> * There are several methods of raising a controlled SMI# via<br> * software, among them:<br>diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c<br>index 950dbe0..64065ae 100644<br>--- a/src/southbridge/intel/ibexpeak/smi.c<br>+++ b/src/southbridge/intel/ibexpeak/smi.c<br>@@ -268,6 +268,7 @@<br> * - on APMC writes (io 0xb2)<br> * - on writes to SLP_EN (sleep states)<br> * - on writes to GBL_RLS (bios commands)<br>+ * - on ACPI TRAP method<br> * No SMIs:<br> * - on microcontroller writes (io 0x62/0x66)<br> */<br>@@ -294,6 +295,10 @@<br> smi_en |= EOS | GBL_SMI_EN;<br> <br> outl(smi_en, pmbase + SMI_EN);<br>+<br>+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */<br>+ RCBA32(IOTR3+4) = 0x000200f0;<br>+ RCBA32(IOTR3+0) = 0x000c0801;<br> }<br> <br> void southbridge_trigger_smi(void)<br>diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c<br>index 8c9cb58..fffb1d9 100644<br>--- a/src/southbridge/intel/lynxpoint/smi.c<br>+++ b/src/southbridge/intel/lynxpoint/smi.c<br>@@ -62,11 +62,16 @@<br> * - on APMC writes (io 0xb2)<br> * - on writes to SLP_EN (sleep states)<br> * - on writes to GBL_RLS (bios commands)<br>+ * - on ACPI TRAP method<br> * No SMIs:<br> * - on microcontroller writes (io 0x62/0x66)<br> * - on TCO events<br> */<br> enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);<br>+<br>+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */<br>+ RCBA32(IOTR3+4) = 0x000200f0;<br>+ RCBA32(IOTR3+0) = 0x000c0801;<br> }<br> <br> void southbridge_trigger_smi(void)<br></pre><p>To view, visit <a href="https://review.coreboot.org/20328">change 20328</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20328"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I14c9cee3da0dac7428b24c049e68b95ce099322f </div>
<div style="display:none"> Gerrit-Change-Number: 20328 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>