[coreboot-gerrit] Change in coreboot[master]: google/kahlee: Add mainboard GPIOs to ACPI

[Marc Jones (Code Review)]

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/20313


Change subject: google/kahlee: Add mainboard GPIOs to ACPI
......................................................................

google/kahlee: Add mainboard GPIOs to ACPI

Add the Google mainboard GPIOs to the ACPI table.

Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/mainboard/google/kahlee/chromeos.c
M src/mainboard/google/kahlee/mainboard.c
2 files changed, 16 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/20313/1

diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c
index f84c618..4112db5 100644
--- a/src/mainboard/google/kahlee/chromeos.c
+++ b/src/mainboard/google/kahlee/chromeos.c
@@ -18,7 +18,10 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <boot/coreboot_tables.h>
 #include <console/console.h>
+#include <soc/gpio.h>
 
+/* SPI Write protect */
+#define CROS_WP_GPIO	GPIO_122
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
@@ -33,5 +36,15 @@
 
 int get_write_protect_state(void)
 {
-	return 0;
+	return gpio_get(CROS_WP_GPIO);
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
 }
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index 639ebbb..0ce4514 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -21,6 +21,7 @@
 #include <ec.h>
 #include "onboard.h"
 #include <smbios.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@@ -112,8 +113,8 @@
 
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = mainboard_smbios_data;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
-
 
 struct chip_operations mainboard_ops = {
 	.enable_dev = kahlee_enable,

-- 
To view, visit https://review.coreboot.org/20313
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1
Gerrit-Change-Number: 20313
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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