<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20313">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/kahlee: Add mainboard GPIOs to ACPI<br><br>Add the Google mainboard GPIOs to the ACPI table.<br><br>Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1<br>Signed-off-by: Marc Jones <marcj303@gmail.com><br>---<br>M src/mainboard/google/kahlee/chromeos.c<br>M src/mainboard/google/kahlee/mainboard.c<br>2 files changed, 16 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/20313/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c<br>index f84c618..4112db5 100644<br>--- a/src/mainboard/google/kahlee/chromeos.c<br>+++ b/src/mainboard/google/kahlee/chromeos.c<br>@@ -18,7 +18,10 @@<br> #include <vendorcode/google/chromeos/chromeos.h><br> #include <boot/coreboot_tables.h><br> #include <console/console.h><br>+#include <soc/gpio.h><br> <br>+/* SPI Write protect */<br>+#define CROS_WP_GPIO       GPIO_122<br> <br> void fill_lb_gpios(struct lb_gpios *gpios)<br> {<br>@@ -33,5 +36,15 @@<br> <br> int get_write_protect_state(void)<br> {<br>-  return 0;<br>+    return gpio_get(CROS_WP_GPIO);<br>+}<br>+<br>+static const struct cros_gpio cros_gpios[] = {<br>+       CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),<br>+  CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),<br>+};<br>+<br>+void mainboard_chromeos_acpi_generate(void)<br>+{<br>+      chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));<br> }<br>diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c<br>index 639ebbb..0ce4514 100644<br>--- a/src/mainboard/google/kahlee/mainboard.c<br>+++ b/src/mainboard/google/kahlee/mainboard.c<br>@@ -21,6 +21,7 @@<br> #include <ec.h><br> #include "onboard.h"<br> #include <smbios.h><br>+#include <vendorcode/google/chromeos/chromeos.h><br> <br> /***********************************************************<br>  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.<br>@@ -112,8 +113,8 @@<br> <br>         dev->ops->init = mainboard_init;<br>        dev->ops->get_smbios_data = mainboard_smbios_data;<br>+     dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;<br> }<br>-<br> <br> struct chip_operations mainboard_ops = {<br>    .enable_dev = kahlee_enable,<br></pre><p>To view, visit <a href="https://review.coreboot.org/20313">change 20313</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20313"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1 </div>
<div style="display:none"> Gerrit-Change-Number: 20313 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>