[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Add GPIO functions to romstage

[Marc Jones (Code Review)]

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/20310


Change subject: soc/amd/stoneyridge: Add GPIO functions to romstage
......................................................................

soc/amd/stoneyridge: Add GPIO functions to romstage

A mainboard may access GPIO in romstage.

Change-Id: Id380c6570943ce2a0bf6112d62cc91aeae283fcf
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/soc/amd/common/Makefile.inc
M src/soc/amd/stoneyridge/Makefile.inc
M src/soc/amd/stoneyridge/include/soc/gpio.h
3 files changed, 4 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/20310/1

diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc
index 78aa1fa..a10d2f7 100644
--- a/src/soc/amd/common/Makefile.inc
+++ b/src/soc/amd/common/Makefile.inc
@@ -27,4 +27,6 @@
 
 subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block
 
+CPPFLAGS_common += -I$(src)/soc/amd/common
+
 endif
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index fdcb57c..1a6e38b 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -48,6 +48,7 @@
 romstage-y += dimmSpd.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 romstage-y += fixme.c
+romstage-y += gpio.c
 romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
 romstage-y += smbus.c
 romstage-y += smbus_spd.c
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index a66701a..0693368 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -58,7 +58,7 @@
 #define   GPIO_42	(GPIO_BANK0_CONTROL + 0xa8)
 
 /* GPIO_64 - GPIO_127 */
-#define GPIO_BANK1 (CONTROL AMD_SB_ACPI_MMIO_ADDR + 0x1600)
+#define GPIO_BANK1_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1600)
 #define   GPIO_64	(GPIO_BANK1_CONTROL + 0x00)
 #define   GPIO_65	(GPIO_BANK1_CONTROL + 0x04)
 #define   GPIO_66	(GPIO_BANK1_CONTROL + 0x08)

-- 
To view, visit https://review.coreboot.org/20310
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id380c6570943ce2a0bf6112d62cc91aeae283fcf
Gerrit-Change-Number: 20310
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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