<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20310">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Add GPIO functions to romstage<br><br>A mainboard may access GPIO in romstage.<br><br>Change-Id: Id380c6570943ce2a0bf6112d62cc91aeae283fcf<br>Signed-off-by: Marc Jones <marcj303@gmail.com><br>---<br>M src/soc/amd/common/Makefile.inc<br>M src/soc/amd/stoneyridge/Makefile.inc<br>M src/soc/amd/stoneyridge/include/soc/gpio.h<br>3 files changed, 4 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/20310/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc<br>index 78aa1fa..a10d2f7 100644<br>--- a/src/soc/amd/common/Makefile.inc<br>+++ b/src/soc/amd/common/Makefile.inc<br>@@ -27,4 +27,6 @@<br> <br> subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block<br> <br>+CPPFLAGS_common += -I$(src)/soc/amd/common<br>+<br> endif<br>diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc<br>index fdcb57c..1a6e38b 100644<br>--- a/src/soc/amd/stoneyridge/Makefile.inc<br>+++ b/src/soc/amd/stoneyridge/Makefile.inc<br>@@ -48,6 +48,7 @@<br> romstage-y += dimmSpd.c<br> romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c<br> romstage-y += fixme.c<br>+romstage-y += gpio.c<br> romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c<br> romstage-y += smbus.c<br> romstage-y += smbus_spd.c<br>diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h<br>index a66701a..0693368 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/gpio.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h<br>@@ -58,7 +58,7 @@<br> #define   GPIO_42  (GPIO_BANK0_CONTROL + 0xa8)<br> <br> /* GPIO_64 - GPIO_127 */<br>-#define GPIO_BANK1 (CONTROL AMD_SB_ACPI_MMIO_ADDR + 0x1600)<br>+#define GPIO_BANK1_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1600)<br> #define   GPIO_64       (GPIO_BANK1_CONTROL + 0x00)<br> #define   GPIO_65 (GPIO_BANK1_CONTROL + 0x04)<br> #define   GPIO_66 (GPIO_BANK1_CONTROL + 0x08)<br></pre><p>To view, visit <a href="https://review.coreboot.org/20310">change 20310</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20310"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id380c6570943ce2a0bf6112d62cc91aeae283fcf </div>
<div style="display:none"> Gerrit-Change-Number: 20310 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>