[coreboot-gerrit] Change in coreboot[master]: include/device: Add pci ids for Intel CNL
Lijian Zhao (Code Review)
gerrit at coreboot.org
Fri Jun 23 01:29:37 CEST 2017
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20308
Change subject: include/device: Add pci ids for Intel CNL
......................................................................
include/device: Add pci ids for Intel CNL
Change-Id: Ia76c391e04e1e11bd110764902b91ef4ed5e8490
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/include/device/pci_ids.h
1 file changed, 64 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/20308/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index bd9b2d5..b7c5668 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2654,7 +2654,6 @@
#define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599
/* Intel Lynx Point Device IDS */
-
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MIN 0x8c41
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MAX 0x8c4f
@@ -2673,6 +2672,9 @@
#define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56
#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8
#define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31e8
+#define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC 0x9d85
+#define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC 0x9d84
+#define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83
/* Intel PCIE device ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10
@@ -2734,18 +2736,39 @@
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23 0xa2ed
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24 0xa2ee
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP1 0x9db8
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP2 0x9db9
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP3 0x9dba
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP4 0x9dbb
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP5 0x9dbc
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP6 0x9dbd
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP7 0x9dbe
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP8 0x9dbf
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP9 0x9db0
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP10 0x9db1
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP11 0x9db2
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP12 0x9db3
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP13 0x9db4
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14 0x9db5
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15 0x9db6
+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16 0x9db7
+
/* Intel SATA device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03
#define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07
#define PCI_DEVICE_ID_INTEL_SPT_KBL_SATA 0x282a
#define PCI_DEVICE_ID_INTEL_APL_SATA 0x5ae0
#define PCI_DEVICE_ID_INTEL_GLK_SATA 0x31e3
+#define PCI_DEVICE_ID_INTEL_CNL_SATA 0x9dd5
+#define PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA 0x9dd7
+#define PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA 0x282a
/* Intel PMC device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21
#define PCI_DEVICE_ID_INTEL_KBP_H_PMC 0xa121
#define PCI_DEVICE_ID_INTEL_APL_PMC 0x5a94
#define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194
+#define PCI_DEVICE_ID_INTEL_CNL_PMC 0x9da1
/* Intel I2C device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60
@@ -2770,6 +2793,12 @@
#define PCI_DEVICE_ID_INTEL_GLK_I2C5 0x31b6
#define PCI_DEVICE_ID_INTEL_GLK_I2C6 0x31b8
#define PCI_DEVICE_ID_INTEL_GLK_I2C7 0x31ba
+#define PCI_DEVICE_ID_INTEL_CNL_I2C0 0x9de8
+#define PCI_DEVICE_ID_INTEL_CNL_I2C1 0x9de9
+#define PCI_DEVICE_ID_INTEL_CNL_I2C2 0x9dea
+#define PCI_DEVICE_ID_INTEL_CNL_I2C3 0x9deb
+#define PCI_DEVICE_ID_INTEL_CNL_I2C4 0x9dc5
+#define PCI_DEVICE_ID_INTEL_CNL_I2C5 0x9dc6
/* Intel UART device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27
@@ -2786,6 +2815,9 @@
#define PCI_DEVICE_ID_INTEL_GLK_UART1 0x31be
#define PCI_DEVICE_ID_INTEL_GLK_UART2 0x31c0
#define PCI_DEVICE_ID_INTEL_GLK_UART3 0x31ee
+#define PCI_DEVICE_ID_INTEL_CNL_UART0 0x9da8
+#define PCI_DEVICE_ID_INTEL_CNL_UART1 0x9da9
+#define PCI_DEVICE_ID_INTEL_CNL_UART2 0x9dc7
/* Intel SPI device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24
@@ -2798,6 +2830,10 @@
#define PCI_DEVICE_ID_INTEL_GLK_SPI0 0x31c2
#define PCI_DEVICE_ID_INTEL_GLK_SPI1 0x31c4
#define PCI_DEVICE_ID_INTEL_GLK_SPI2 0x31c6
+#define PCI_DEVICE_ID_INTEL_CNL_SPI0 0x9daa
+#define PCI_DEVICE_ID_INTEL_CNL_SPI1 0x9dab
+#define PCI_DEVICE_ID_INTEL_CNL_SPI2 0x9dfb
+#define PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI 0x9da4
/* Intel IGD device Ids */
#define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906
@@ -2813,6 +2849,14 @@
#define PCI_DEVICE_ID_INTEL_APL_IGD_HD_505 0x5a84
#define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500 0x5a85
#define PCI_DEVICE_ID_INTEL_GLK_IGD 0x3184
+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1 0x5A51
+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2 0x5A59
+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3 0x5A41
+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4 0x5A49
+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1 0x5A52
+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2 0x5A5A
+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3 0x5A42
+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A
/* Intel Northbridge Ids */
#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
@@ -2826,42 +2870,61 @@
#define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c
#define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910
#define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914
+#define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04
+#define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23
#define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123
+#define PCI_DEVICE_ID_INTEL_CNL_SMBUS 0x9da3
/* Intel XHCI device Ids */
#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
#define PCI_DEVICE_ID_INTEL_GLK_XHCI 0x31a8
#define PCI_DEVICE_ID_INTEL_SPT_LP_XHCI 0x9d2f
#define PCI_DEVICE_ID_INTEL_KBP_H_XHCI 0xa12f
+#define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded
/* Intel P2SB device Ids */
#define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92
#define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192
+#define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0
/* Intel SRAM device Ids */
#define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec
#define PCI_DEVICE_ID_INTEL_GLK_SRAM 0x31ec
+#define PCI_DEVICE_ID_INTEL_CNL_SRAM 0x9def
/* Intel AUDIO device Ids */
#define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98
#define PCI_DEVICE_ID_INTEL_GLK_AUDIO 0x3198
+#define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8
/* Intel HECI/ME device Ids */
#define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a
#define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a
+#define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0
/* Intel XDCI device Ids */
#define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa
#define PCI_DEVICE_ID_INTEL_GLK_XDCI 0x31aa
#define PCI_DEVICE_ID_INTEL_SPT_LP_XDCI 0x9d30
+#define PCI_DEVICE_ID_INTEL_CNL_LP_XDCI 0x9dee
/* Intel SD device Ids */
#define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
#define PCI_DEVICE_ID_INTEL_SKL_SD 0x9d2d
+#define PCI_DEVICE_ID_INTEL_CNL_SD 0x9df5
+
+/* Intel PCH Ids */
+#define PCH_CNL_LP_M_SUPER 0x9d80
+#define PCH_CNL_LP_M_SUPER_UNLOCK 0x9d81
+#define PCH_CNL_LP_M_SUPER_LOCK 0x9d82
+#define PCH_CNL_LP_Y_PREMIUM 0x9d83
+#define PCH_CNL_LP_U_PREMIUM 0x9d84
+#define PCH_CNL_LP_U_BASE 0x9d85
+#define PCH_CNL_H_DT_SUPER 0xa280
#define PCI_VENDOR_ID_COMPUTONE 0x8e0e
#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291
--
To view, visit https://review.coreboot.org/20308
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia76c391e04e1e11bd110764902b91ef4ed5e8490
Gerrit-Change-Number: 20308
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170622/d67b5ceb/attachment.html>
More information about the coreboot-gerrit
mailing list