<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20308">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">include/device: Add pci ids for Intel CNL<br><br>Change-Id: Ia76c391e04e1e11bd110764902b91ef4ed5e8490<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/include/device/pci_ids.h<br>1 file changed, 64 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/20308/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h<br>index bd9b2d5..b7c5668 100644<br>--- a/src/include/device/pci_ids.h<br>+++ b/src/include/device/pci_ids.h<br>@@ -2654,7 +2654,6 @@<br> #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599<br> <br> /* Intel Lynx Point Device IDS */<br>-<br> #define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MIN 0x8c41<br> #define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MAX 0x8c4f<br> <br>@@ -2673,6 +2672,9 @@<br> #define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56<br> #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8<br> #define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31e8<br>+#define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC 0x9d85<br>+#define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC 0x9d84<br>+#define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83<br> <br> /* Intel PCIE device ids */<br> #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10<br>@@ -2734,18 +2736,39 @@<br> #define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23 0xa2ed<br> #define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24 0xa2ee<br> <br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP1 0x9db8<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP2 0x9db9<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP3 0x9dba<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP4 0x9dbb<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP5 0x9dbc<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP6 0x9dbd<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP7 0x9dbe<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP8 0x9dbf<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP9 0x9db0<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP10 0x9db1<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP11 0x9db2<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP12 0x9db3<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP13 0x9db4<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14 0x9db5<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15 0x9db6<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16 0x9db7<br>+<br> /* Intel SATA device Ids */<br> #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03<br> #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07<br> #define PCI_DEVICE_ID_INTEL_SPT_KBL_SATA 0x282a<br> #define PCI_DEVICE_ID_INTEL_APL_SATA 0x5ae0<br> #define PCI_DEVICE_ID_INTEL_GLK_SATA 0x31e3<br>+#define PCI_DEVICE_ID_INTEL_CNL_SATA 0x9dd5<br>+#define PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA 0x9dd7<br>+#define PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA 0x282a<br> <br> /* Intel PMC device Ids */<br> #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21<br> #define PCI_DEVICE_ID_INTEL_KBP_H_PMC 0xa121<br> #define PCI_DEVICE_ID_INTEL_APL_PMC 0x5a94<br> #define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194<br>+#define PCI_DEVICE_ID_INTEL_CNL_PMC 0x9da1<br> <br> /* Intel I2C device Ids */<br> #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60<br>@@ -2770,6 +2793,12 @@<br> #define PCI_DEVICE_ID_INTEL_GLK_I2C5 0x31b6<br> #define PCI_DEVICE_ID_INTEL_GLK_I2C6 0x31b8<br> #define PCI_DEVICE_ID_INTEL_GLK_I2C7 0x31ba<br>+#define PCI_DEVICE_ID_INTEL_CNL_I2C0 0x9de8<br>+#define PCI_DEVICE_ID_INTEL_CNL_I2C1 0x9de9<br>+#define PCI_DEVICE_ID_INTEL_CNL_I2C2 0x9dea<br>+#define PCI_DEVICE_ID_INTEL_CNL_I2C3 0x9deb<br>+#define PCI_DEVICE_ID_INTEL_CNL_I2C4 0x9dc5<br>+#define PCI_DEVICE_ID_INTEL_CNL_I2C5 0x9dc6<br> <br> /* Intel UART device Ids */<br> #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27<br>@@ -2786,6 +2815,9 @@<br> #define PCI_DEVICE_ID_INTEL_GLK_UART1 0x31be<br> #define PCI_DEVICE_ID_INTEL_GLK_UART2 0x31c0<br> #define PCI_DEVICE_ID_INTEL_GLK_UART3 0x31ee<br>+#define PCI_DEVICE_ID_INTEL_CNL_UART0 0x9da8<br>+#define PCI_DEVICE_ID_INTEL_CNL_UART1 0x9da9<br>+#define PCI_DEVICE_ID_INTEL_CNL_UART2 0x9dc7<br> <br> /* Intel SPI device Ids */<br> #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24<br>@@ -2798,6 +2830,10 @@<br> #define PCI_DEVICE_ID_INTEL_GLK_SPI0 0x31c2<br> #define PCI_DEVICE_ID_INTEL_GLK_SPI1 0x31c4<br> #define PCI_DEVICE_ID_INTEL_GLK_SPI2 0x31c6<br>+#define PCI_DEVICE_ID_INTEL_CNL_SPI0 0x9daa<br>+#define PCI_DEVICE_ID_INTEL_CNL_SPI1 0x9dab<br>+#define PCI_DEVICE_ID_INTEL_CNL_SPI2 0x9dfb<br>+#define PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI 0x9da4<br> <br> /* Intel IGD device Ids */<br> #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906<br>@@ -2813,6 +2849,14 @@<br> #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_505 0x5a84<br> #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500 0x5a85<br> #define PCI_DEVICE_ID_INTEL_GLK_IGD 0x3184<br>+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1 0x5A51<br>+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2 0x5A59<br>+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3 0x5A41<br>+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4 0x5A49<br>+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1 0x5A52<br>+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2 0x5A5A<br>+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3 0x5A42<br>+#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A<br> <br> /* Intel Northbridge Ids */<br> #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0<br>@@ -2826,42 +2870,61 @@<br> #define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c<br> #define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910<br> #define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914<br>+#define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04<br>+#define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02<br> <br> /* Intel SMBUS device Ids */<br> #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23<br> #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123<br>+#define PCI_DEVICE_ID_INTEL_CNL_SMBUS 0x9da3<br> <br> /* Intel XHCI device Ids */<br> #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8<br> #define PCI_DEVICE_ID_INTEL_GLK_XHCI 0x31a8<br> #define PCI_DEVICE_ID_INTEL_SPT_LP_XHCI 0x9d2f<br> #define PCI_DEVICE_ID_INTEL_KBP_H_XHCI 0xa12f<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded<br> <br> /* Intel P2SB device Ids */<br> #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92<br> #define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192<br>+#define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0<br> <br> /* Intel SRAM device Ids */<br> #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec<br> #define PCI_DEVICE_ID_INTEL_GLK_SRAM 0x31ec<br>+#define PCI_DEVICE_ID_INTEL_CNL_SRAM 0x9def<br> <br> /* Intel AUDIO device Ids */<br> #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98<br> #define PCI_DEVICE_ID_INTEL_GLK_AUDIO 0x3198<br>+#define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8<br> <br> /* Intel HECI/ME device Ids */<br> #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a<br> #define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a<br>+#define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0<br> <br> /* Intel XDCI device Ids */<br> #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa<br> #define PCI_DEVICE_ID_INTEL_GLK_XDCI 0x31aa<br> #define PCI_DEVICE_ID_INTEL_SPT_LP_XDCI 0x9d30<br>+#define PCI_DEVICE_ID_INTEL_CNL_LP_XDCI 0x9dee<br> <br> /* Intel SD device Ids */<br> #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca<br> #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca<br> #define PCI_DEVICE_ID_INTEL_SKL_SD 0x9d2d<br>+#define PCI_DEVICE_ID_INTEL_CNL_SD 0x9df5<br>+<br>+/* Intel PCH Ids */<br>+#define PCH_CNL_LP_M_SUPER 0x9d80<br>+#define PCH_CNL_LP_M_SUPER_UNLOCK 0x9d81<br>+#define PCH_CNL_LP_M_SUPER_LOCK 0x9d82<br>+#define PCH_CNL_LP_Y_PREMIUM 0x9d83<br>+#define PCH_CNL_LP_U_PREMIUM 0x9d84<br>+#define PCH_CNL_LP_U_BASE 0x9d85<br>+#define PCH_CNL_H_DT_SUPER 0xa280<br> <br> #define PCI_VENDOR_ID_COMPUTONE 0x8e0e<br> #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291<br></pre><p>To view, visit <a href="https://review.coreboot.org/20308">change 20308</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20308"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia76c391e04e1e11bd110764902b91ef4ed5e8490 </div>
<div style="display:none"> Gerrit-Change-Number: 20308 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>