[coreboot-gerrit] Change in coreboot[master]: link southbridge/amd/rs780/early_setup.c
Arthur Heymans (Code Review)
gerrit at coreboot.org
Wed Jun 21 15:58:38 CEST 2017
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20297
Change subject: link southbridge/amd/rs780/early_setup.c
......................................................................
link southbridge/amd/rs780/early_setup.c
Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/advansus/a785e-i/romstage.c
M src/mainboard/amd/bimini_fam10/romstage.c
M src/mainboard/amd/mahogany/romstage.c
M src/mainboard/amd/mahogany_fam10/romstage.c
M src/mainboard/amd/tilapia_fam10/romstage.c
M src/mainboard/asrock/939a785gmh/romstage.c
M src/mainboard/asus/m4a78-em/romstage.c
M src/mainboard/asus/m4a785-m/romstage.c
M src/mainboard/asus/m5a88-v/romstage.c
M src/mainboard/avalue/eax-785e/romstage.c
M src/mainboard/gigabyte/ma785gm/romstage.c
M src/mainboard/gigabyte/ma785gmt/romstage.c
M src/mainboard/gigabyte/ma78gm/romstage.c
M src/mainboard/iei/kino-780am2-fam10/romstage.c
M src/mainboard/jetway/pa78vm5/romstage.c
M src/southbridge/amd/rs780/Makefile.inc
M src/southbridge/amd/rs780/early_setup.c
M src/southbridge/amd/rs780/rs780.h
18 files changed, 40 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/20297/1
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index f145c25..ce7221c 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -41,7 +41,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <southbridge/amd/sb800/smbus.h>
#include <southbridge/amd/sb800/sb800.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c"
#include <arch/early_variables.h>
#include <cbmem.h>
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index cdb12e3..bc9c790 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -41,7 +41,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c"
#include <spd.h>
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index a8e54d5..77acdf3 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -46,7 +46,7 @@
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index efb2885..15dc111 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -46,7 +46,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
@@ -216,7 +216,6 @@
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 022e91d..63e10eb 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -45,7 +45,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index bd74fde..086e588 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -48,7 +48,7 @@
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 1076bf6..1aba202 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -46,7 +46,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 40334d6..135dd4c 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -47,7 +47,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index d11f98a..f9b2119 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -44,7 +44,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c"
#include "spd.h"
#include <reset.h>
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 4648310..d5f0955 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -44,7 +44,7 @@
#include <cbmem.h>
#include "spd.h"
#include <reset.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c"
#include "resourcemap.c"
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 2e22556..a06d949 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -43,7 +43,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index bf51e38..6bc58c1 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -43,7 +43,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 1405507..12bb735 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -46,7 +46,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 1731ef4..4bb46f6 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -46,7 +46,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index f540a73..c27e38e 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -47,7 +47,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc
index b02f45b..36086e9 100644
--- a/src/southbridge/amd/rs780/Makefile.inc
+++ b/src/southbridge/amd/rs780/Makefile.inc
@@ -1,5 +1,7 @@
ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS780),y)
+romstage-y += early_setup.c
+
ramstage-y += rs780.c
ramstage-y += cmn.c
ramstage-y += pcie.c
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index b0a40be..2268eb8 100644
--- a/src/southbridge/amd/rs780/early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -13,7 +13,13 @@
* GNU General Public License for more details.
*/
+#include <types.h>
+#include <arch/io.h>
+#include <northbridge/amd/amdmct/mct/mct_d.h>
+#include <console/console.h>
+
#include "rev.h"
+#include "rs780.h"
#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
#define NBMISC_INDEX 0x60
@@ -31,37 +37,37 @@
pci_write_config32(dev, index_reg + 0x4, data);
}
-static u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
+u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
{
return nb_read_index((nb_dev), NBMISC_INDEX, (index));
}
-static void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
+void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
{
nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
}
-static u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
+u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
{
return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
}
-static void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
+void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
{
nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
}
-static u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
+u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
{
return nb_read_index((nb_dev), NBMC_INDEX, (index));
}
-static void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
+void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
{
nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
}
-static void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
+void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
@@ -73,7 +79,7 @@
}
}
-static void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
+void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
@@ -85,7 +91,7 @@
}
}
-static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
+void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
@@ -114,7 +120,7 @@
#endif
-static void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask,
+void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask,
u8 val)
{
u8 reg_old, reg;
@@ -126,7 +132,7 @@
}
}
-static void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
+void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
@@ -155,25 +161,6 @@
}
#endif
-static u8 get_nb_rev(pci_devfn_t nb_dev)
-{
- u8 reg;
- reg = pci_read_config8(nb_dev, 0x89); /* copy from CIM, can't find in doc */
- switch(reg & 3)
- {
- case 0x01:
- reg = REV_RS780_A12;
- break;
- case 0x02:
- reg = REV_RS780_A13;
- break;
- default:
- reg = REV_RS780_A11;
- break;
- }
- return reg;
-}
-
/*****************************************
* Init HT link speed/width for rs780 -- k8 link
* 1: Check CPU Family, Family10?
@@ -198,7 +185,7 @@
[0xe] = 0xC6, /* 2.6GHz HyperTransport 3 only */
};
-static void rs780_htinit(void)
+void rs780_htinit(void)
{
/*
* About HT, it has been done in enumerate_ht_chain().
@@ -610,16 +597,12 @@
}
/* enable CFG access to Dev8, which is the SB P2P Bridge */
-static void enable_rs780_dev8(void)
+void enable_rs780_dev8(void)
{
set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
}
-static void rs780_before_pci_init(void)
-{
-}
-
-static void rs780_early_setup(void)
+void rs780_early_setup(void)
{
pci_devfn_t nb_dev = PCI_DEV(0, 0, 0);
printk(BIOS_INFO, "rs780_early_setup()\n");
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index 31bec9a..37c88e2 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -210,4 +210,7 @@
int is_family0Fh(void);
int is_family10h(void);
void pcie_hide_unused_ports(device_t nb_dev);
+void enable_rs780_dev8(void);
+void rs780_early_setup(void);
+void rs780_htinit(void);
#endif /* __RS780_H__ */
--
To view, visit https://review.coreboot.org/20297
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f
Gerrit-Change-Number: 20297
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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