<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20297">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">link southbridge/amd/rs780/early_setup.c<br><br>Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/advansus/a785e-i/romstage.c<br>M src/mainboard/amd/bimini_fam10/romstage.c<br>M src/mainboard/amd/mahogany/romstage.c<br>M src/mainboard/amd/mahogany_fam10/romstage.c<br>M src/mainboard/amd/tilapia_fam10/romstage.c<br>M src/mainboard/asrock/939a785gmh/romstage.c<br>M src/mainboard/asus/m4a78-em/romstage.c<br>M src/mainboard/asus/m4a785-m/romstage.c<br>M src/mainboard/asus/m5a88-v/romstage.c<br>M src/mainboard/avalue/eax-785e/romstage.c<br>M src/mainboard/gigabyte/ma785gm/romstage.c<br>M src/mainboard/gigabyte/ma785gmt/romstage.c<br>M src/mainboard/gigabyte/ma78gm/romstage.c<br>M src/mainboard/iei/kino-780am2-fam10/romstage.c<br>M src/mainboard/jetway/pa78vm5/romstage.c<br>M src/southbridge/amd/rs780/Makefile.inc<br>M src/southbridge/amd/rs780/early_setup.c<br>M src/southbridge/amd/rs780/rs780.h<br>18 files changed, 40 insertions(+), 53 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/20297/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c<br>index f145c25..ce7221c 100644<br>--- a/src/mainboard/advansus/a785e-i/romstage.c<br>+++ b/src/mainboard/advansus/a785e-i/romstage.c<br>@@ -41,7 +41,7 @@<br> #include <cpu/amd/family_10h-family_15h/init_cpus.h><br> #include <southbridge/amd/sb800/smbus.h><br> #include <southbridge/amd/sb800/sb800.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> #include "southbridge/amd/sb800/early_setup.c"<br> #include <arch/early_variables.h><br> #include <cbmem.h><br>diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c<br>index cdb12e3..bc9c790 100644<br>--- a/src/mainboard/amd/bimini_fam10/romstage.c<br>+++ b/src/mainboard/amd/bimini_fam10/romstage.c<br>@@ -41,7 +41,7 @@<br> #include <cpu/amd/family_10h-family_15h/init_cpus.h><br> #include <arch/early_variables.h><br> #include <cbmem.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> #include "southbridge/amd/sb800/early_setup.c"<br> #include <spd.h><br> <br>diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c<br>index a8e54d5..77acdf3 100644<br>--- a/src/mainboard/amd/mahogany/romstage.c<br>+++ b/src/mainboard/amd/mahogany/romstage.c<br>@@ -46,7 +46,7 @@<br> return do_smbus_read_byte(SMBUS_IO_BASE, device, address);<br> }<br> <br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> #include <northbridge/amd/amdk8/amdk8.h><br> #include "northbridge/amd/amdk8/incoherent_ht.c"<br> #include "lib/generic_sdram.c"<br>diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c<br>index efb2885..15dc111 100644<br>--- a/src/mainboard/amd/mahogany_fam10/romstage.c<br>+++ b/src/mainboard/amd/mahogany_fam10/romstage.c<br>@@ -46,7 +46,7 @@<br> #include <cpu/amd/family_10h-family_15h/init_cpus.h><br> #include <arch/early_variables.h><br> #include <cbmem.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> #include <spd.h><br> <br> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)<br>@@ -216,7 +216,6 @@<br> <br> // die("After MCT init before CAR disabled.");<br> <br>- rs780_before_pci_init();<br> sb7xx_51xx_before_pci_init();<br> <br> post_code(0x42);<br>diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c<br>index 022e91d..63e10eb 100644<br>--- a/src/mainboard/amd/tilapia_fam10/romstage.c<br>+++ b/src/mainboard/amd/tilapia_fam10/romstage.c<br>@@ -45,7 +45,7 @@<br> #include <arch/early_variables.h><br> #include <cbmem.h><br> #include <spd.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> <br> #include "resourcemap.c"<br> #include "cpu/amd/quadcore/quadcore.c"<br>diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c<br>index bd74fde..086e588 100644<br>--- a/src/mainboard/asrock/939a785gmh/romstage.c<br>+++ b/src/mainboard/asrock/939a785gmh/romstage.c<br>@@ -48,7 +48,7 @@<br> return do_smbus_read_byte(SMBUS_IO_BASE, device, address);<br> }<br> <br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> #include <northbridge/amd/amdk8/amdk8.h><br> #include "northbridge/amd/amdk8/incoherent_ht.c"<br> #include "northbridge/amd/amdk8/raminit.c"<br>diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c<br>index 1076bf6..1aba202 100644<br>--- a/src/mainboard/asus/m4a78-em/romstage.c<br>+++ b/src/mainboard/asus/m4a78-em/romstage.c<br>@@ -46,7 +46,7 @@<br> #include <arch/early_variables.h><br> #include <cbmem.h><br> #include <spd.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> <br> #include "resourcemap.c"<br> #include "cpu/amd/quadcore/quadcore.c"<br>diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c<br>index 40334d6..135dd4c 100644<br>--- a/src/mainboard/asus/m4a785-m/romstage.c<br>+++ b/src/mainboard/asus/m4a785-m/romstage.c<br>@@ -47,7 +47,7 @@<br> #include <arch/early_variables.h><br> #include <cbmem.h><br> #include <spd.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> <br> #include "resourcemap.c"<br> #include "cpu/amd/quadcore/quadcore.c"<br>diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c<br>index d11f98a..f9b2119 100644<br>--- a/src/mainboard/asus/m5a88-v/romstage.c<br>+++ b/src/mainboard/asus/m5a88-v/romstage.c<br>@@ -44,7 +44,7 @@<br> #include <cpu/amd/family_10h-family_15h/init_cpus.h><br> #include <arch/early_variables.h><br> #include <cbmem.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> #include "southbridge/amd/sb800/early_setup.c"<br> #include "spd.h"<br> #include <reset.h><br>diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c<br>index 4648310..d5f0955 100644<br>--- a/src/mainboard/avalue/eax-785e/romstage.c<br>+++ b/src/mainboard/avalue/eax-785e/romstage.c<br>@@ -44,7 +44,7 @@<br> #include <cbmem.h><br> #include "spd.h"<br> #include <reset.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> #include "southbridge/amd/sb800/early_setup.c"<br> <br> #include "resourcemap.c"<br>diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c<br>index 2e22556..a06d949 100644<br>--- a/src/mainboard/gigabyte/ma785gm/romstage.c<br>+++ b/src/mainboard/gigabyte/ma785gm/romstage.c<br>@@ -43,7 +43,7 @@<br> #include <arch/early_variables.h><br> #include <cbmem.h><br> #include <spd.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> <br> #include "resourcemap.c"<br> #include "cpu/amd/quadcore/quadcore.c"<br>diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c<br>index bf51e38..6bc58c1 100644<br>--- a/src/mainboard/gigabyte/ma785gmt/romstage.c<br>+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c<br>@@ -43,7 +43,7 @@<br> #include <arch/early_variables.h><br> #include <cbmem.h><br> #include <spd.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> <br> #include "resourcemap.c"<br> #include "cpu/amd/quadcore/quadcore.c"<br>diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c<br>index 1405507..12bb735 100644<br>--- a/src/mainboard/gigabyte/ma78gm/romstage.c<br>+++ b/src/mainboard/gigabyte/ma78gm/romstage.c<br>@@ -46,7 +46,7 @@<br> #include <cpu/amd/family_10h-family_15h/init_cpus.h><br> #include <arch/early_variables.h><br> #include <cbmem.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> <br> #include "resourcemap.c"<br> #include "cpu/amd/quadcore/quadcore.c"<br>diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c<br>index 1731ef4..4bb46f6 100644<br>--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c<br>+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c<br>@@ -46,7 +46,7 @@<br> #include <cpu/amd/family_10h-family_15h/init_cpus.h><br> #include <arch/early_variables.h><br> #include <cbmem.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> <br> #include "resourcemap.c"<br> #include "cpu/amd/quadcore/quadcore.c"<br>diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c<br>index f540a73..c27e38e 100644<br>--- a/src/mainboard/jetway/pa78vm5/romstage.c<br>+++ b/src/mainboard/jetway/pa78vm5/romstage.c<br>@@ -47,7 +47,7 @@<br> #include <cpu/amd/family_10h-family_15h/init_cpus.h><br> #include <arch/early_variables.h><br> #include <cbmem.h><br>-#include "southbridge/amd/rs780/early_setup.c"<br>+#include <southbridge/amd/rs780/rs780.h><br> <br> #include "resourcemap.c"<br> #include "cpu/amd/quadcore/quadcore.c"<br>diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc<br>index b02f45b..36086e9 100644<br>--- a/src/southbridge/amd/rs780/Makefile.inc<br>+++ b/src/southbridge/amd/rs780/Makefile.inc<br>@@ -1,5 +1,7 @@<br> ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS780),y)<br> <br>+romstage-y += early_setup.c<br>+<br> ramstage-y += rs780.c<br> ramstage-y += cmn.c<br> ramstage-y += pcie.c<br>diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c<br>index b0a40be..2268eb8 100644<br>--- a/src/southbridge/amd/rs780/early_setup.c<br>+++ b/src/southbridge/amd/rs780/early_setup.c<br>@@ -13,7 +13,13 @@<br> * GNU General Public License for more details.<br> */<br> <br>+#include <types.h><br>+#include <arch/io.h><br>+#include <northbridge/amd/amdmct/mct/mct_d.h><br>+#include <console/console.h><br>+<br> #include "rev.h"<br>+#include "rs780.h"<br> <br> #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */<br> #define NBMISC_INDEX 0x60<br>@@ -31,37 +37,37 @@<br> pci_write_config32(dev, index_reg + 0x4, data);<br> }<br> <br>-static u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)<br>+u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)<br> {<br> return nb_read_index((nb_dev), NBMISC_INDEX, (index));<br> }<br> <br>-static void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)<br>+void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)<br> {<br> nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));<br> }<br> <br>-static u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)<br>+u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)<br> {<br> return nb_read_index((nb_dev), NBHTIU_INDEX, (index));<br> }<br> <br>-static void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)<br>+void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)<br> {<br> nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));<br> }<br> <br>-static u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)<br>+u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)<br> {<br> return nb_read_index((nb_dev), NBMC_INDEX, (index));<br> }<br> <br>-static void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)<br>+void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)<br> {<br> nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));<br> }<br> <br>-static void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,<br>+void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,<br> u32 val)<br> {<br> u32 reg_old, reg;<br>@@ -73,7 +79,7 @@<br> }<br> }<br> <br>-static void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,<br>+void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,<br> u32 val)<br> {<br> u32 reg_old, reg;<br>@@ -85,7 +91,7 @@<br> }<br> }<br> <br>-static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,<br>+void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,<br> u32 val)<br> {<br> u32 reg_old, reg;<br>@@ -114,7 +120,7 @@<br> #endif<br> <br> <br>-static void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask,<br>+void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask,<br> u8 val)<br> {<br> u8 reg_old, reg;<br>@@ -126,7 +132,7 @@<br> }<br> }<br> <br>-static void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,<br>+void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,<br> u32 val)<br> {<br> u32 reg_old, reg;<br>@@ -155,25 +161,6 @@<br> }<br> #endif<br> <br>-static u8 get_nb_rev(pci_devfn_t nb_dev)<br>-{<br>- u8 reg;<br>- reg = pci_read_config8(nb_dev, 0x89); /* copy from CIM, can't find in doc */<br>- switch(reg & 3)<br>- {<br>- case 0x01:<br>- reg = REV_RS780_A12;<br>- break;<br>- case 0x02:<br>- reg = REV_RS780_A13;<br>- break;<br>- default:<br>- reg = REV_RS780_A11;<br>- break;<br>- }<br>- return reg;<br>-}<br>-<br> /*****************************************<br> * Init HT link speed/width for rs780 -- k8 link<br> * 1: Check CPU Family, Family10?<br>@@ -198,7 +185,7 @@<br> [0xe] = 0xC6, /* 2.6GHz HyperTransport 3 only */<br> };<br> <br>-static void rs780_htinit(void)<br>+void rs780_htinit(void)<br> {<br> /*<br> * About HT, it has been done in enumerate_ht_chain().<br>@@ -610,16 +597,12 @@<br> }<br> <br> /* enable CFG access to Dev8, which is the SB P2P Bridge */<br>-static void enable_rs780_dev8(void)<br>+void enable_rs780_dev8(void)<br> {<br> set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);<br> }<br> <br>-static void rs780_before_pci_init(void)<br>-{<br>-}<br>-<br>-static void rs780_early_setup(void)<br>+void rs780_early_setup(void)<br> {<br> pci_devfn_t nb_dev = PCI_DEV(0, 0, 0);<br> printk(BIOS_INFO, "rs780_early_setup()\n");<br>diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h<br>index 31bec9a..37c88e2 100644<br>--- a/src/southbridge/amd/rs780/rs780.h<br>+++ b/src/southbridge/amd/rs780/rs780.h<br>@@ -210,4 +210,7 @@<br> int is_family0Fh(void);<br> int is_family10h(void);<br> void pcie_hide_unused_ports(device_t nb_dev);<br>+void enable_rs780_dev8(void);<br>+void rs780_early_setup(void);<br>+void rs780_htinit(void);<br> #endif /* __RS780_H__ */<br></pre><p>To view, visit <a href="https://review.coreboot.org/20297">change 20297</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20297"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f </div>
<div style="display:none"> Gerrit-Change-Number: 20297 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>