[coreboot-gerrit] Change in coreboot[master]: haswell: add CBMEM_MEMINFO table when initing RAM

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19958 )

Change subject: haswell: add CBMEM_MEMINFO table when initing RAM
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Patch Set 2:

(4 comments)

https://review.coreboot.org/#/c/19958/2/src/northbridge/intel/haswell/raminit.c
File src/northbridge/intel/haswell/raminit.c:

https://review.coreboot.org/#/c/19958/2/src/northbridge/intel/haswell/raminit.c@203
PS2, Line 203: 0x18
MEMORY_TYPE_DDR is implemented in include/smbios.h


https://review.coreboot.org/#/c/19958/2/src/northbridge/intel/haswell/raminit.c@210
PS2, Line 210: 122
Adding a include/spd_ddr3.h file similar to the spd_ddr2.h file for these fields would be nice.


https://review.coreboot.org/#/c/19958/2/src/northbridge/intel/haswell/raminit.c@218
PS2, Line 218: //SPD_SODIMM
Should we detect this, or will this code only be for laptops?


https://review.coreboot.org/#/c/19958/2/src/northbridge/intel/haswell/raminit.c@218
PS2, Line 218:  3
Is this an SPD field or a SMBIOS field?  Use a #define?



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1
Gerrit-Change-Number: 19958
Gerrit-PatchSet: 2
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude at gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Wed, 07 Jun 2017 18:02:08 +0000
Gerrit-HasComments: Yes