[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Sort Kconfig for Cannonlake

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20828


Change subject: soc/intel/cannonlake: Sort Kconfig for Cannonlake
......................................................................

soc/intel/cannonlake: Sort Kconfig for Cannonlake

Look and feel update, sort the sequence in Kconfig.

Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 15 insertions(+), 15 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/20828/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 1c0f1bf..471fe6c 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -8,37 +8,37 @@
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_BOOTBLOCK_X86_32
-	select ARCH_VERSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
-	select SOC_INTEL_COMMON_BLOCK_TIMER
-	select HAVE_MONOTONIC_TIMER
-	select TSC_CONSTANT_RATE
-	select TSC_MONOTONIC_TIMER
-	select UDELAY_TSC
-	select REG_SCRIPT
+	select ARCH_VERSTAGE_X86_32
 	select C_ENVIRONMENT_BOOTBLOCK
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select HAVE_HARD_RESET
 	select HAVE_INTEL_FIRMWARE
+	select HAVE_MONOTONIC_TIMER
 	select INTEL_CAR_NEM_ENHANCED
 	select PLATFORM_USES_FSP2_0
+	select REG_SCRIPT
 	select RELOCATABLE_RAMSTAGE
 	select SOC_INTEL_COMMON
-	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_CAR
 	select SOC_INTEL_COMMON_BLOCK_CPU
-	select SOC_INTEL_COMMON_RESET
-	select SOC_INTEL_COMMON_BLOCK_LPSS
-	select SOC_INTEL_COMMON_BLOCK_UART
-	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
-	select SOC_INTEL_COMMON_BLOCK_PCR
-	select SOC_INTEL_COMMON_BLOCK_SMBUS
-	select SOC_INTEL_COMMON_BLOCK_RTC
 	select SOC_INTEL_COMMON_BLOCK_CSE
+	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
 	select SOC_INTEL_COMMON_BLOCK_GPIO
+	select SOC_INTEL_COMMON_BLOCK_LPSS
+	select SOC_INTEL_COMMON_BLOCK_PCR
+	select SOC_INTEL_COMMON_BLOCK_RTC
+	select SOC_INTEL_COMMON_BLOCK_SA
+	select SOC_INTEL_COMMON_BLOCK_SMBUS
+	select SOC_INTEL_COMMON_BLOCK_TIMER
+	select SOC_INTEL_COMMON_BLOCK_UART
+	select SOC_INTEL_COMMON_RESET
 	select SUPPORT_CPU_UCODE_IN_CBFS
+	select TSC_CONSTANT_RATE
+	select TSC_MONOTONIC_TIMER
+	select UDELAY_TSC
 
 config UART_DEBUG
 	bool "Enable UART debug port."

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70
Gerrit-Change-Number: 20828
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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