<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20828">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Sort Kconfig for Cannonlake<br><br>Look and feel update, sort the sequence in Kconfig.<br><br>Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>1 file changed, 15 insertions(+), 15 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/20828/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig<br>index 1c0f1bf..471fe6c 100644<br>--- a/src/soc/intel/cannonlake/Kconfig<br>+++ b/src/soc/intel/cannonlake/Kconfig<br>@@ -8,37 +8,37 @@<br> config CPU_SPECIFIC_OPTIONS<br> def_bool y<br> select ARCH_BOOTBLOCK_X86_32<br>- select ARCH_VERSTAGE_X86_32<br> select ARCH_RAMSTAGE_X86_32<br> select ARCH_ROMSTAGE_X86_32<br>- select SOC_INTEL_COMMON_BLOCK_TIMER<br>- select HAVE_MONOTONIC_TIMER<br>- select TSC_CONSTANT_RATE<br>- select TSC_MONOTONIC_TIMER<br>- select UDELAY_TSC<br>- select REG_SCRIPT<br>+ select ARCH_VERSTAGE_X86_32<br> select C_ENVIRONMENT_BOOTBLOCK<br> select CPU_INTEL_FIRMWARE_INTERFACE_TABLE<br> select HAVE_HARD_RESET<br> select HAVE_INTEL_FIRMWARE<br>+ select HAVE_MONOTONIC_TIMER<br> select INTEL_CAR_NEM_ENHANCED<br> select PLATFORM_USES_FSP2_0<br>+ select REG_SCRIPT<br> select RELOCATABLE_RAMSTAGE<br> select SOC_INTEL_COMMON<br>- select SOC_INTEL_COMMON_BLOCK_SA<br> select SOC_INTEL_COMMON_BLOCK<br> select SOC_INTEL_COMMON_BLOCK_CAR<br> select SOC_INTEL_COMMON_BLOCK_CPU<br>- select SOC_INTEL_COMMON_RESET<br>- select SOC_INTEL_COMMON_BLOCK_LPSS<br>- select SOC_INTEL_COMMON_BLOCK_UART<br>- select SOC_INTEL_COMMON_BLOCK_FAST_SPI<br>- select SOC_INTEL_COMMON_BLOCK_PCR<br>- select SOC_INTEL_COMMON_BLOCK_SMBUS<br>- select SOC_INTEL_COMMON_BLOCK_RTC<br> select SOC_INTEL_COMMON_BLOCK_CSE<br>+ select SOC_INTEL_COMMON_BLOCK_FAST_SPI<br> select SOC_INTEL_COMMON_BLOCK_GPIO<br>+ select SOC_INTEL_COMMON_BLOCK_LPSS<br>+ select SOC_INTEL_COMMON_BLOCK_PCR<br>+ select SOC_INTEL_COMMON_BLOCK_RTC<br>+ select SOC_INTEL_COMMON_BLOCK_SA<br>+ select SOC_INTEL_COMMON_BLOCK_SMBUS<br>+ select SOC_INTEL_COMMON_BLOCK_TIMER<br>+ select SOC_INTEL_COMMON_BLOCK_UART<br>+ select SOC_INTEL_COMMON_RESET<br> select SUPPORT_CPU_UCODE_IN_CBFS<br>+ select TSC_CONSTANT_RATE<br>+ select TSC_MONOTONIC_TIMER<br>+ select UDELAY_TSC<br> <br> config UART_DEBUG<br> bool "Enable UART debug port."<br></pre><p>To view, visit <a href="https://review.coreboot.org/20828">change 20828</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20828"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70 </div>
<div style="display:none"> Gerrit-Change-Number: 20828 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>