[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Clarify BAR mask in SPI base
Marshall Dawson (Code Review)
gerrit at coreboot.org
Thu Jul 27 18:21:26 CEST 2017
Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/20790
Change subject: soc/amd/stoneyridge: Clarify BAR mask in SPI base
......................................................................
soc/amd/stoneyridge: Clarify BAR mask in SPI base
The format of the D14F3xA0 SPI Base_Addr register is different
than a traditional BAR. Change the function to preserve any
enables already in place. Change the AND mask to remove the
reserved field and the enables.
Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/early_setup.c
1 file changed, 6 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/20790/1
diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c
index 68bccc4..ca3447f 100644
--- a/src/soc/amd/stoneyridge/early_setup.c
+++ b/src/soc/amd/stoneyridge/early_setup.c
@@ -242,13 +242,16 @@
{
/* Make sure the base address is predictable */
device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
+ u32 base, enables;
- u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER)
- & 0xfffffff0;
+ base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
+ enables = base & 0xf;
+ base &= ~0x3f;
+
if (!base) {
base = SPI_BASE_ADDRESS;
pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base
- | SPI_ROM_ENABLE);
+ | enables | SPI_ROM_ENABLE);
/* PCI_COMMAND_MEMORY is read-only and enabled. */
}
return (uintptr_t)base;
--
To view, visit https://review.coreboot.org/20790
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5
Gerrit-Change-Number: 20790
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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