<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20790">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Clarify BAR mask in SPI base<br><br>The format of the D14F3xA0 SPI Base_Addr register is different<br>than a traditional BAR.  Change the function to preserve any<br>enables already in place.  Change the AND mask to remove the<br>reserved field and the enables.<br><br>Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/early_setup.c<br>1 file changed, 6 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/20790/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c<br>index 68bccc4..ca3447f 100644<br>--- a/src/soc/amd/stoneyridge/early_setup.c<br>+++ b/src/soc/amd/stoneyridge/early_setup.c<br>@@ -242,13 +242,16 @@<br> {<br>      /* Make sure the base address is predictable */<br>       device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);<br>+        u32 base, enables;<br> <br>-        u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER)<br>-                                                      & 0xfffffff0;<br>+    base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);<br>+ enables = base & 0xf;<br>+    base &= ~0x3f;<br>+<br>         if (!base) {<br>          base = SPI_BASE_ADDRESS;<br>              pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base<br>-                                                   | SPI_ROM_ENABLE);<br>+                                           | enables | SPI_ROM_ENABLE);<br>          /* PCI_COMMAND_MEMORY is read-only and enabled. */<br>    }<br>     return (uintptr_t)base;<br></pre><p>To view, visit <a href="https://review.coreboot.org/20790">change 20790</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20790"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5 </div>
<div style="display:none"> Gerrit-Change-Number: 20790 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>